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AJvYcCW5MvDT1Ud5s0MWXgQC0nnRz5T4KP/s3fznNrdMsFZSTsazZ0kG5vvff/4/Bszbxf00pCAlIizcSncyQg==@lists.infradead.org X-Gm-Message-State: AOJu0YwRRIqZ4uLYdC1FSV9aegK6hC2ylJJUblzWHoTh4lCWNKsBc5GC RRLsXPixUb3qHO0Cm8Dh4A2CBZQ53KAQdANjgv2JXNOlV1VM/Ljr X-Google-Smtp-Source: AGHT+IFpvbKAGMcBFfuBrPC9vCpoH+zVcNDvH81Wljcvo2dEo6JSn4vRv3yO5yMxJ/YDoSwbgcxnyw== X-Received: by 2002:a05:6a00:9282:b0:71e:587d:f268 with SMTP id d2e1a72fcca58-71edbbc153bmr2884829b3a.4.1729569761875; Mon, 21 Oct 2024 21:02:41 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71ec1338c80sm3718457b3a.48.2024.10.21.21.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 21:02:41 -0700 (PDT) From: Inochi Amaoto To: Chen Wang , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Inochi Amaoto , Geert Uytterhoeven , Lad Prabhakar , Yangyu Chen , Hal Feng Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v4 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI Date: Tue, 22 Oct 2024 12:02:15 +0800 Message-ID: <20241022040218.450573-2-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241022040218.450573-1-inochiama@gmail.com> References: <20241022040218.450573-1-inochiama@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241021_210243_489172_065D7034 X-CRM114-Status: GOOD ( 14.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully featured ACLINT device. This ACLINT has an extra SSWI field to support fast S-mode IPI. Add necessary compatible string for the T-HEAD ACLINT sswi device. Signed-off-by: Inochi Amaoto Reviewed-by: Conor Dooley --- .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml new file mode 100644 index 000000000000..0106fbf3ea1f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device + +maintainers: + - Inochi Amaoto + +description: + The SSWI device is a part of the riscv ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a RISC-V + platform. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. + +properties: + compatible: + items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 0 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; + reg = <0x94000000 0x00004000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + }; +...