| Message ID | 20241028033928.223218-2-nick.hu@sifive.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support SSTC while PM operations | expand |
On Mon, Oct 28, 2024 at 9:09 AM Nick Hu <nick.hu@sifive.com> wrote: > > If the HW support the SSTC extension, we should save and restore the > stimecmp register while cpu non retention suspend. > > Signed-off-by: Nick Hu <nick.hu@sifive.com> LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/include/asm/suspend.h | 4 ++++ > arch/riscv/kernel/suspend.c | 14 ++++++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h > index 4ffb022b097f..dc5782b5fbad 100644 > --- a/arch/riscv/include/asm/suspend.h > +++ b/arch/riscv/include/asm/suspend.h > @@ -18,6 +18,10 @@ struct suspend_context { > unsigned long ie; > #ifdef CONFIG_MMU > unsigned long satp; > + unsigned long stimecmp; > +#if __riscv_xlen < 64 > + unsigned long stimecmph; > +#endif > #endif > }; > > diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c > index 9a8a0dc035b2..24b3f57d467f 100644 > --- a/arch/riscv/kernel/suspend.c > +++ b/arch/riscv/kernel/suspend.c > @@ -30,6 +30,13 @@ void suspend_save_csrs(struct suspend_context *context) > */ > > #ifdef CONFIG_MMU > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { > + context->stimecmp = csr_read(CSR_STIMECMP); > +#if __riscv_xlen < 64 > + context->stimecmph = csr_read(CSR_STIMECMPH); > +#endif > + } > + > context->satp = csr_read(CSR_SATP); > #endif > } > @@ -43,6 +50,13 @@ void suspend_restore_csrs(struct suspend_context *context) > csr_write(CSR_IE, context->ie); > > #ifdef CONFIG_MMU > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { > + csr_write(CSR_STIMECMP, context->stimecmp); > +#if __riscv_xlen < 64 > + csr_write(CSR_STIMECMPH, context->stimecmph); > +#endif > + } > + > csr_write(CSR_SATP, context->satp); > #endif > } > -- > 2.34.1 > >
diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 4ffb022b097f..dc5782b5fbad 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -18,6 +18,10 @@ struct suspend_context { unsigned long ie; #ifdef CONFIG_MMU unsigned long satp; + unsigned long stimecmp; +#if __riscv_xlen < 64 + unsigned long stimecmph; +#endif #endif }; diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 9a8a0dc035b2..24b3f57d467f 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -30,6 +30,13 @@ void suspend_save_csrs(struct suspend_context *context) */ #ifdef CONFIG_MMU + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { + context->stimecmp = csr_read(CSR_STIMECMP); +#if __riscv_xlen < 64 + context->stimecmph = csr_read(CSR_STIMECMPH); +#endif + } + context->satp = csr_read(CSR_SATP); #endif } @@ -43,6 +50,13 @@ void suspend_restore_csrs(struct suspend_context *context) csr_write(CSR_IE, context->ie); #ifdef CONFIG_MMU + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { + csr_write(CSR_STIMECMP, context->stimecmp); +#if __riscv_xlen < 64 + csr_write(CSR_STIMECMPH, context->stimecmph); +#endif + } + csr_write(CSR_SATP, context->satp); #endif }
If the HW support the SSTC extension, we should save and restore the stimecmp register while cpu non retention suspend. Signed-off-by: Nick Hu <nick.hu@sifive.com> --- arch/riscv/include/asm/suspend.h | 4 ++++ arch/riscv/kernel/suspend.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+)