diff mbox series

[v6,11/13] riscv: Add ISA extension parsing for Ziccrse

Message ID 20241103145153.105097-12-alexghiti@rivosinc.com (mailing list archive)
State Accepted
Commit 2d36fe89d872f1e655670280ce13a8dbe9d366a7
Headers show
Series Zacas/Zabha support and qspinlocks | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail PR summary
conchuod/patch-11-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh took 141.27s
conchuod/patch-11-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh took 1932.12s
conchuod/patch-11-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh took 2131.04s
conchuod/patch-11-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh took 20.40s
conchuod/patch-11-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh took 22.34s
conchuod/patch-11-test-6 success .github/scripts/patches/tests/checkpatch.sh took 0.61s
conchuod/patch-11-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh took 43.56s
conchuod/patch-11-test-8 success .github/scripts/patches/tests/header_inline.sh took 0.01s
conchuod/patch-11-test-9 success .github/scripts/patches/tests/kdoc.sh took 0.49s
conchuod/patch-11-test-10 success .github/scripts/patches/tests/module_param.sh took 0.01s
conchuod/patch-11-test-11 success .github/scripts/patches/tests/verify_fixes.sh took 0.00s
conchuod/patch-11-test-12 success .github/scripts/patches/tests/verify_signedoff.sh took 0.03s

Commit Message

Alexandre Ghiti Nov. 3, 2024, 2:51 p.m. UTC
Add support to parse the Ziccrse string in the riscv,isa string.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 74bcb0e2bd1f..0aa3c3f5e682 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -94,6 +94,7 @@ 
 #define RISCV_ISA_EXT_ZAWRS		85
 #define RISCV_ISA_EXT_SVVPTC		86
 #define RISCV_ISA_EXT_ZABHA		87
+#define RISCV_ISA_EXT_ZICCRSE		88
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 5e743d8d34f5..5f453a039ec9 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -314,6 +314,7 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 					  riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts,
 					  riscv_ext_zicboz_validate),
+	__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
 	__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
 	__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
 	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),