From patchwork Tue Nov 5 18:35:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Valentina Fernandez X-Patchwork-Id: 13863449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F449D33A22 for ; Tue, 5 Nov 2024 18:42:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IXinzYZdYOLWyrjKUtRAcisKkkLNYQMZkJGYqfLAv1M=; b=PCZ/NvaU9meWdh KhTGJJeNcID6Mx4Gurowc/a77afqMAzXaaAwyhdJl3mBNfbU+zpUJTDixvykDJc/hT4RmKAZsic09 ij+7g2O17eQcruDqubJQ3AshNpC2pc36ZypVxcwdtHrKPoxp34yv5973/CdQX5hqvAy30ZlG9kasO NHn/pBAmEy8VrCSXacTnYWoQufEhEm7fYAVxRwUTBFbD9qo8qK2CgphXPUHlo4wgzqDyCxeBR4ZVB 96wHvx1fyLqbqQv6nbeRvZhxBrUWQp2p+BHW3Z0XjFnDKhbfns1bPTP25ck+tzmSHSYhfAsT1jGtG Lzfz7mawgL1G0Fu/2T/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t8OV8-00000000PmH-1iaI; Tue, 05 Nov 2024 18:42:02 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t8OPl-00000000OES-2SUh for linux-riscv@lists.infradead.org; Tue, 05 Nov 2024 18:36:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1730831789; x=1762367789; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o3lz7dS/0X/IsotdugNCOPCUgilgkWwAiXObrss6PhM=; b=PbE6aoxQnCiBrCUjnMPIlVAZKYlBsyg1GfJaxe4iA03IhqzXODVSL7bo vTrmJ1OMQBQCvYtdTqQZ4U1kDWq7QFKMfu1GWDI0Q4NfMQV+mUp1/UaT9 8J35ryCWGHWTH/HP90HkL99Gttb5PWF12dBmatMVnej5a1dgq7r2PkpEW Xk6fImPWU8wN5i9NtW7BnvFuS0uoX/wGS95SE8UgPbKNJqBwb0VB3MBUR HJITm+661MEa86rnDktrH+gmEYQ5TFiJ6Zw/8VaYXH+RyIRFtQavJIB3a 5Jo+Qz0ibVq9SZKEJGhRrkHVY0vreri1Jgl7YHdwuaJ9Lq4VpzcBavp7V Q==; X-CSE-ConnectionGUID: T1uVhdVNQzWREZUebUBC5w== X-CSE-MsgGUID: jf9X/ks1T1CHW9+cqU6PUA== X-IronPort-AV: E=Sophos;i="6.11,260,1725346800"; d="scan'208";a="37385617" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 05 Nov 2024 11:36:25 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 5 Nov 2024 11:36:24 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 5 Nov 2024 11:36:21 -0700 From: Valentina Fernandez To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v3 3/4] dt-bindings: mailbox: add binding for Microchip IPC mailbox controller Date: Tue, 5 Nov 2024 18:35:12 +0000 Message-ID: <20241105183513.1358736-4-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105183513.1358736-1-valentina.fernandezalanis@microchip.com> References: <20241105183513.1358736-1-valentina.fernandezalanis@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241105_103629_678286_C623AC55 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a dt-binding for the Microchip Inter-Processor Communication (IPC) mailbox controller. Signed-off-by: Valentina Fernandez --- .../bindings/mailbox/microchip,sbi-ipc.yaml | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml new file mode 100644 index 000000000000..9e67c09e4bea --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Inter-processor communication (IPC) mailbox controller + +maintainers: + - Valentina Fernandez + +description: + The Microchip Inter-processor Communication (IPC) facilitates + message passing between processors using an interrupt signaling + mechanism. + +properties: + compatible: + oneOf: + - description: + Intended for use by software running in supervisor privileged + mode (s-mode). This SBI interface is compatible with the Mi-V + Inter-hart Communication (IHC) IP. + items: + - const: microchip,sbi-ipc + + - description: + SoC-specific compatible, intended for use by the SBI + implementation in machine mode (m-mode). + items: + - const: microchip,miv-ihc-rtl-v2 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 5 + + interrupt-names: + minItems: 1 + maxItems: 5 + items: + pattern: "^hart-[0-5]+$" + + "#mbox-cells": + description: > + For the SBI "device", the cell represents the global "logical" channel IDs. + The meaning of channel IDs are platform firmware dependent. + + For the SoC-specific compatible string, the cell represents the physical + channel and does not vary based on the platform firmware. + const: 1 + + microchip,ihc-chan-disabled-mask: + description: > + Represents the enable/disable state of the bi-directional IHC + channels within the MIV-IHC IP configuration. + + The mask is a 16-bit value, but only the first 15 bits are utilized. + Each of the bits corresponds to one of the 15 IHC channels. + + A bit set to '1' indicates that the corresponding channel is disabled, + and any read or write operations to that channel will return zero. + + A bit set to '0' indicates that the corresponding channel is enabled + and will be accessible through its dedicated address range registers. + + The remaining bit of the 16-bit mask is reserved and should be ignored. + + The actual enable/disable state of each channel is determined by the + IP block’s configuration. + $ref: /schemas/types.yaml#/definitions/uint16 + default: 0 + +required: + - compatible + - interrupts + - interrupt-names + - "#mbox-cells" + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: microchip,sbi-ipc + then: + properties: + reg: false + microchip,ihc-chan-disabled-mask: false + else: + required: + - reg + - microchip,ihc-chan-disabled-mask + +examples: + - | + mailbox { + compatible = "microchip,sbi-ipc"; + interrupt-parent = <&plic>; + interrupts = <180>, <179>, <178>; + interrupt-names = "hart-1", "hart-2", "hart-3"; + #mbox-cells = <1>; + }; + - | + mailbox@50000000 { + compatible = "microchip,miv-ihc-rtl-v2"; + microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; + reg = <0x50000000 0x1C000>; + interrupt-parent = <&plic>; + interrupts = <180>, <179>, <178>; + interrupt-names = "hart-1", "hart-2", "hart-3"; + #mbox-cells = <1>; + };