| Message ID | 20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 0eb512779d642b21ced83778287a0f7a3ca8f2a1 |
| Headers | show |
| Series | [for-next,v2] riscv: Fix default misaligned access trap | expand |
On 11/8/24 18:47, Charlie Jenkins wrote: > Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses > supported") removed the default handlers for handle_misaligned_load() > and handle_misaligned_store(). When the kernel is compiled without > RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing > compilation errors. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Jesse Taube <mr.bossman075@gmail.com> Thanks, Jesse > Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported") > --- > Changes in v2: > - Change CONFIG_RISCV_SCALAR_MISALIGNED to CONFIG_RISCV_MISALIGNED > (Jesse) > - Link to v1: https://lore.kernel.org/r/20241107-fix_handle_misaligned_load-v1-1-07d7852c9991@rivosinc.com > --- > arch/riscv/include/asm/entry-common.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h > index 7b32d2b08bb6..b28ccc6cdeea 100644 > --- a/arch/riscv/include/asm/entry-common.h > +++ b/arch/riscv/include/asm/entry-common.h > @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, > void handle_page_fault(struct pt_regs *regs); > void handle_break(struct pt_regs *regs); > > +#ifdef CONFIG_RISCV_MISALIGNED > int handle_misaligned_load(struct pt_regs *regs); > int handle_misaligned_store(struct pt_regs *regs); > +#else > +static inline int handle_misaligned_load(struct pt_regs *regs) > +{ > + return -1; > +} > + > +static inline int handle_misaligned_store(struct pt_regs *regs) > +{ > + return -1; > +} > +#endif > > #endif /* _ASM_RISCV_ENTRY_COMMON_H */ > > --- > base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2 > change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Fri, 08 Nov 2024 15:47:36 -0800 you wrote: > Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses > supported") removed the default handlers for handle_misaligned_load() > and handle_misaligned_store(). When the kernel is compiled without > RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing > compilation errors. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported") > > [...] Here is the summary with links: - [for-next,v2] riscv: Fix default misaligned access trap https://git.kernel.org/riscv/c/0eb512779d64 You are awesome, thank you!
diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index 7b32d2b08bb6..b28ccc6cdeea 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, void handle_page_fault(struct pt_regs *regs); void handle_break(struct pt_regs *regs); +#ifdef CONFIG_RISCV_MISALIGNED int handle_misaligned_load(struct pt_regs *regs); int handle_misaligned_store(struct pt_regs *regs); +#else +static inline int handle_misaligned_load(struct pt_regs *regs) +{ + return -1; +} + +static inline int handle_misaligned_store(struct pt_regs *regs) +{ + return -1; +} +#endif #endif /* _ASM_RISCV_ENTRY_COMMON_H */
Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported") removed the default handlers for handle_misaligned_load() and handle_misaligned_store(). When the kernel is compiled without RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing compilation errors. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported") --- Changes in v2: - Change CONFIG_RISCV_SCALAR_MISALIGNED to CONFIG_RISCV_MISALIGNED (Jesse) - Link to v1: https://lore.kernel.org/r/20241107-fix_handle_misaligned_load-v1-1-07d7852c9991@rivosinc.com --- arch/riscv/include/asm/entry-common.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) --- base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2 change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e