| Message ID | 20250102204137.423081-2-e@freeshell.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 | expand |
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0d8339357bad..0bc922b3ae8a 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock { #clock-cells = <0>; }; + timer { + compatible = "riscv, timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>;
no idea if this does anything useful; not needed for boot Signed-off-by: E Shattow <e@freeshell.de> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)