diff mbox series

[v4,4/4] riscv: dts: spacemit: Add clock controller for K1

Message ID 20250103215636.19967-6-heylenay@4d2.org (mailing list archive)
State New
Headers show
Series Add clock controller support for SpacemiT K1 | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Commit Message

Haylen Chu Jan. 3, 2025, 9:56 p.m. UTC 
Add clock controllers for APBC, APBS, APMU and MPMU regions along with
system controllers which they belong to.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 97 ++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 0777bf9e0118..a2cd141f9177 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -3,6 +3,8 @@ 
  * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
  */
 
+#include <dt-bindings/clock/spacemit,k1-ccu.h>
+
 /dts-v1/;
 / {
 	#address-cells = <2>;
@@ -318,6 +320,40 @@  cluster1_l2_cache: l2-cache1 {
 		};
 	};
 
+	clocks {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		vctcxo_1m: clock-1m {
+			compatible = "fixed-clock";
+			clock-frequency = <1000000>;
+			clock-output-names = "vctcxo_1m";
+			#clock-cells = <0>;
+		};
+
+		vctcxo_24m: clock-24m {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "vctcxo_24m";
+			#clock-cells = <0>;
+		};
+
+		vctcxo_3m: clock-3m {
+			compatible = "fixed-clock";
+			clock-frequency = <3000000>;
+			clock-output-names = "vctcxo_3m";
+			#clock-cells = <0>;
+		};
+
+		osc_32k: clock-32k {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "osc_32k";
+			#clock-cells = <0>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -326,6 +362,21 @@  soc {
 		dma-noncoherent;
 		ranges;
 
+		syscon_apbc: system-control@d4015000 {
+			compatible = "spacemit,k1-apbc-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4015000 0x0 0x1000>;
+
+			clk_apbc: clock-controller {
+				compatible = "spacemit,k1-ccu-apbc";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				#clock-cells = <1>;
+			};
+		};
+
 		uart0: serial@d4017000 {
 			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017000 0x0 0x100>;
@@ -416,6 +467,52 @@  uart9: serial@d4017800 {
 			status = "disabled";
 		};
 
+		syscon_mpmu: system-control@d4050000 {
+			compatible = "spacemit,k1-mpmu-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4050000 0x0 0x209c>;
+
+			clk_mpmu: clock-controller {
+				compatible = "spacemit,k1-ccu-mpmu";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				#clock-cells = <1>;
+			};
+		};
+
+		syscon_apbs: system-control@d4090000 {
+			compatible = "spacemit,k1-apbs-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4090000 0x0 0x1000>;
+
+			clk_apbs: clock-controller {
+				compatible = "spacemit,k1-ccu-apbs";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				spacemit,mpmu = <&syscon_mpmu>;
+				#clock-cells = <1>;
+			};
+		};
+
+		syscon_apmu: system-control@d4282800 {
+			compatible = "spacemit,k1-apmu-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4282800 0x0 0x400>;
+
+			clk_apmu: clock-controller {
+				compatible = "spacemit,k1-ccu-apmu";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				#clock-cells = <1>;
+			};
+		};
+
 		plic: interrupt-controller@e0000000 {
 			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xe0000000 0x0 0x4000000>;