From patchwork Sun Jan 5 08:39:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Kondratiev X-Patchwork-Id: 13926456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43A9EE77197 for ; Sun, 5 Jan 2025 08:40:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qW5jhNbrusGIw485EU/dzlLrp6941ekVmJ+pNwHC4uI=; b=u533a7qGhazl6A m5xfYvwd1kDJhrquNOSN2c4KG1wAMp8HqGc0ZP2t0KkOEJeygBPCfUr1w1dlvFUkSS33zWpzhc58P cU4aB0UTLrcI9xDKiLOddv7X8DX5zsxHJpcpyWaC8edcv6KTzIYw/Fc6tgiDsDZGvmp58CZX28XCa GdoGlwPDRf/DuHC4/GoMYrxssJhjicKipguqMCneTI1+V9JTWS8RLqNbPSWTJoIoG7xK4JZb+Mini 4Hge4hfMNBGP1mW1KRH4PCfcaaoCzrwaR2gP5YHlufFWkgoR2kKDllV4UmkRB9DfSLmz8JVjHA3dB VBdnXek+g1lFCAXtd6qw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tUMB2-0000000GY8S-2xVg; Sun, 05 Jan 2025 08:40:04 +0000 Received: from esa4.hc555-34.eu.iphmx.com ([207.54.77.171]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tUMAy-0000000GY7R-2s7j for linux-riscv@lists.infradead.org; Sun, 05 Jan 2025 08:40:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1736066399; x=1767602399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z/K0SqeHgdhQcv49IYilM/zZ3lHXS5Gvf9N0LFcoCU4=; b=m5cgI7CALSTSTVy+SxVuJvhmHrYznJHkppsJumAMuFtUUJsBHlWXuAzz SSpJ/5rMIfCGqj/7UjpWTpXgqSzti9FKFwJlkBDv3qvrdpEE6dvvo1Y0g EwBFA874Fz/lBL5olhdyLNsVHGvWBC76eCF2b+Kkj7yqDneO35ujPc0dU b+RQVDgUzmfvMVAuMY1KLCDmEYj0/i/NQVBFvvHYopdmEp4/3c4iQQ9NX INgTNCaXMrGWf9P5y0yqgD5gmc5IiOg36qZAx+yECRDt9kVMizJgJXn0D JRNHf3CGU2ABsx1lpjTwnfoYGIINCLGjZEv2XbKYjtsB+fPKr4QR1JS6W Q==; X-CSE-ConnectionGUID: CfpY9T+PR9GKa0NAaEl5ag== X-CSE-MsgGUID: hjRKhnmFQwy8mNY0yyKm0A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces01_data.me-corp.lan) ([146.255.191.134]) by esa4.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2025 10:39:51 +0200 X-CSE-ConnectionGUID: XSsLCryfQ2Ke3UGOxo8zcA== X-CSE-MsgGUID: ClLY1LQXRn2Ji/nVT3b89w== Received: from unknown (HELO epgd022.me-corp.lan) ([10.154.54.6]) by ces01_data.me-corp.lan with SMTP; 05 Jan 2025 10:39:51 +0200 Received: by epgd022.me-corp.lan (sSMTP sendmail emulation); Sun, 05 Jan 2025 10:39:51 +0200 From: Vladimir Kondratiev To: Anup Patel , Thomas Gleixner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Vladimir Kondratiev Subject: [PATCH v2] irqchip/riscv-aplic: add support for hart indexes Date: Sun, 5 Jan 2025 10:39:22 +0200 Message-ID: <20250105083922.3563784-1-vladimir.kondratiev@mobileye.com> In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250105_004001_201577_4025136B X-CRM114-Status: GOOD ( 19.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Risc-V APLIC specification defines "hart index" in [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, this document says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indexes specified in optional APLIC property "riscv,hart-index" that should be array of u32 elements, one per interrupt target. If this property not specified, fallback is to use logical hart indexes within the domain. [1]: https://github.com/riscv/riscv-aia Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel --- drivers/irqchip/irq-riscv-aplic-direct.c | 25 +++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c index 7cd6b646774b..c80a65c1732a 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -31,7 +31,7 @@ struct aplic_direct { }; struct aplic_idc { - unsigned int hart_index; + u32 hart_index; void __iomem *regs; struct aplic_direct *direct; }; @@ -219,6 +219,21 @@ static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, return 0; } +static int aplic_direct_get_hart_index(struct device *dev, u32 logical_index, + u32 *hart_index) +{ + static const char *prop_hart_index = "riscv,hart-index"; + struct device_node *np = to_of_node(dev->fwnode); + + if (!np || !of_property_present(np, prop_hart_index)) { + *hart_index = logical_index; + return 0; + } + + return of_property_read_u32_index(np, prop_hart_index, + logical_index, hart_index); +} + int aplic_direct_setup(struct device *dev, void __iomem *regs) { int i, j, rc, cpu, current_cpu, setup_count = 0; @@ -265,8 +280,12 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) cpumask_set_cpu(cpu, &direct->lmask); idc = per_cpu_ptr(&aplic_idcs, cpu); - idc->hart_index = i; - idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + rc = aplic_direct_get_hart_index(dev, i, &idc->hart_index); + if (rc) { + dev_warn(dev, "hart index not found for IDC%d\n", i); + continue; + } + idc->regs = priv->regs + APLIC_IDC_BASE + idc->hart_index * APLIC_IDC_SIZE; idc->direct = direct; aplic_idc_set_delivery(idc, true);