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Mon, 13 Jan 2025 07:09:46 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 1/5] irqchip/riscv-intc: Balance priority and fairness during irq handling Date: Mon, 13 Jan 2025 23:09:29 +0800 Message-Id: <20250113150933.65121-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_070947_745089_2B2E8426 X-CRM114-Status: GOOD ( 12.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Both csr cause and csr topi record the pending bit with the highest priority. If interrupts with high priority arrive frequently within a certain period of time, the interrupts with low priority won't get a chance to be handled. For example, if external interrupts and software interrupts arrive very frequently, the timer interrupts will never be handled. Then buddy watchdog on a buddy CPU will report a hardlockup on the current CPU while current CPU actually can receive irq. This commit solves this problem by handling all pending irqs in a round. During each round, this commit handles pending irqs by their priority. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-intc.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f653c13de62b..bc2ec26aa9e9 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -26,20 +26,40 @@ static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG; static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG; static unsigned int riscv_intc_custom_nr_irqs __ro_after_init; +static unsigned int riscv_prio_irqs[] = { +#ifdef CONFIG_RISCV_M_MODE + IRQ_M_EXT, IRQ_M_SOFT, IRQ_M_TIMER, +#endif + IRQ_S_EXT, IRQ_S_SOFT, IRQ_S_TIMER, IRQ_S_GEXT, + IRQ_VS_EXT, IRQ_VS_SOFT, IRQ_VS_TIMER, + IRQ_PMU_OVF, +}; + static void riscv_intc_irq(struct pt_regs *regs) { - unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; - - if (generic_handle_domain_irq(intc_domain, cause)) - pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause); + unsigned long pending = csr_read(CSR_IP) & csr_read(CSR_IE); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(riscv_prio_irqs); i++) + if (pending & (1UL << riscv_prio_irqs[i])) + if (generic_handle_domain_irq(intc_domain, riscv_prio_irqs[i])) + pr_warn_ratelimited("Failed to handle interrupt (cause: %u)\n", + riscv_prio_irqs[i]); } static void riscv_intc_aia_irq(struct pt_regs *regs) { unsigned long topi; + unsigned long pending; + unsigned int i; + + while ((topi = csr_read(CSR_TOPI))) { + pending = csr_read(CSR_IP) & csr_read(CSR_IE); - while ((topi = csr_read(CSR_TOPI))) - generic_handle_domain_irq(intc_domain, topi >> TOPI_IID_SHIFT); + for (i = 0; i < ARRAY_SIZE(riscv_prio_irqs); i++) + if (pending & (1UL << riscv_prio_irqs[i])) + generic_handle_domain_irq(intc_domain, riscv_prio_irqs[i]); + } } /*