@@ -603,6 +603,7 @@ config RISCV_ISA_SVPBMT
depends on 64BIT && MMU
depends on RISCV_ALTERNATIVE
default y
+ select DMA_DIRECT_REMAP
help
Adds support to dynamically detect the presence of the Svpbmt
ISA-extension (Supervisor-mode: page-based memory types) and
@@ -787,7 +788,6 @@ config RISCV_ISA_ZICBOM
depends on RISCV_ALTERNATIVE
default y
select RISCV_DMA_NONCOHERENT
- select DMA_DIRECT_REMAP
help
Adds support to dynamically detect the presence of the ZICBOM
extension (Cache Block Management Operations) and enable its
@@ -86,6 +86,7 @@ config ERRATA_THEAD_MAE
bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
depends on ERRATA_THEAD && 64BIT && MMU
select RISCV_ALTERNATIVE_EARLY
+ select DMA_DIRECT_REMAP
default y
help
This will apply the memory attribute extension errata to handle the
@@ -96,7 +97,6 @@ config ERRATA_THEAD_MAE
config ERRATA_THEAD_CMO
bool "Apply T-Head cache management errata"
depends on ERRATA_THEAD && MMU
- select DMA_DIRECT_REMAP
select RISCV_DMA_NONCOHERENT
select RISCV_NONSTANDARD_CACHE_OPS
default y
Select DMA_DIRECT_REMAP for the RISC-V extensions that allow to set page-based memory types in PTEs according to the requested DMA attributes. This is the purpose of Svpbmt or XTheadMae extensions. Zicbom or XTheadCmo serve a different purpose, providing instructions to flush/invalidate cache blocks. Fixes: 381cae169853 ("riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT") Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> --- arch/riscv/Kconfig | 2 +- arch/riscv/Kconfig.errata | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)