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Thu, 16 Jan 2025 15:10:31 -0800 (PST) From: Rajnesh Kanwal To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: linux-perf-users@vger.kernel.org, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, ajones@ventanamicro.com, anup@brainfault.org, acme@kernel.org, atishp@rivosinc.com, beeman@rivosinc.com, brauner@kernel.org, conor@kernel.org, heiko@sntech.de, irogers@google.com, mingo@redhat.com, james.clark@arm.com, renyu.zj@linux.alibaba.com, jolsa@kernel.org, jisheng.teoh@starfivetech.com, palmer@dabbelt.com, will@kernel.org, kaiwenxue1@gmail.com, vincent.chen@sifive.com, Rajnesh Kanwal Subject: [PATCH v2 4/7] dt-bindings: riscv: add Sxctr ISA extension description Date: Thu, 16 Jan 2025 23:09:52 +0000 Message-Id: <20250116230955.867152-5-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250116230955.867152-1-rkanwal@rivosinc.com> References: <20250116230955.867152-1-rkanwal@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250116_151033_389194_85B45D13 X-CRM114-Status: UNSURE ( 8.11 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the S[m|s]ctr ISA extension description. Signed-off-by: Rajnesh Kanwal --- .../devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 848354e3048f..8322503f0773 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -167,6 +167,13 @@ properties: extension allows other ISA extension to use indirect CSR access mechanism in M-mode. + - const: smctr + description: | + The standard Smctr supervisor-level extension for the machine mode + to enable recording limited branch history in a register-accessible + internal core storage. Smctr depend on both the implementation of + S-mode and the Sscsrind extension. + - const: sscsrind description: | The standard Sscsrind supervisor-level extension extends the @@ -193,6 +200,13 @@ properties: and mode-based filtering as ratified at commit 01d1df0 ("Add ability to manually trigger workflow. (#2)") of riscv-count-overflow. + - const: ssctr + description: | + The standard Ssctr supervisor-level extension enables recording of + limited branch history in a register-accessible internal core + storage. Ssctr depend on both the implementation of S-mode and the + Sscsrind extension. + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as