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Mon, 27 Jan 2025 21:00:13 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:13 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:56 -0800 Subject: [PATCH v3 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented MIME-Version: 1.0 Message-Id: <20250127-counter_delegation-v3-15-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Charlie Jenkins X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250127_210014_314284_76ADE590 X-CRM114-Status: GOOD ( 17.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Charlie Jenkins When the PMU SBI extension is not implemented, sbi_v2_available should not be set to true. The SBI implementation for counter config matching and firmware counter read should also be skipped when the SBI extension is not implemented. Signed-off-by: Atish Patra Signed-off-by: Charlie Jenkins --- drivers/perf/riscv_pmu_dev.c | 49 +++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index e075d0d15221..52d927576c9b 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -410,18 +410,22 @@ static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) } } -static void rvpmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_check_std_events(struct work_struct *work) { - for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) - rvpmu_sbi_check_event(&pmu_hw_event_map[i]); - - for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) - for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) - for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) - rvpmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); + if (riscv_pmu_sbi_available()) { + for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); + + for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) + for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) + for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) + rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); + } else { + DO_ONCE_LITE_IF(1, pr_err, "Boot time config matching not required for smcdeleg\n"); + } } -static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_check_std_events); static ssize_t rvpmu_format_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -549,6 +553,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) cflags = rvpmu_sbi_get_filter_flags(event); + if (!riscv_pmu_sbi_available()) + return -ENOENT; + /* * In legacy mode, we have to force the fixed counters for those events * but not in the user access mode as we want to use the other counters @@ -562,10 +569,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; ctr_mask = BIT(CSR_INSTRET - CSR_CYCLE); } - } - - if (pmu_sbi_is_fw_event(event) && cdeleg_available) + } else if (pmu_sbi_is_fw_event(event) && cdeleg_available) { ctr_mask = firmware_cmask; + } /* retrieve the available counter index */ #if defined(CONFIG_32BIT) @@ -871,7 +877,7 @@ static u64 rvpmu_ctr_read(struct perf_event *event) return val; } - if (pmu_sbi_is_fw_event(event)) { + if (pmu_sbi_is_fw_event(event) && riscv_pmu_sbi_available()) { ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); if (ret.error) @@ -1524,9 +1530,8 @@ static int rvpmu_event_map(struct perf_event *event, u64 *econfig) config1 = event->attr.config1; if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) return rvpmu_cdeleg_event_map(event, econfig); - } else { + else return rvpmu_sbi_event_map(event, econfig); - } } static int rvpmu_ctr_get_idx(struct perf_event *event) @@ -1944,14 +1949,16 @@ static int __init rvpmu_devinit(void) int ret; struct platform_device *pdev; - if (sbi_spec_version >= sbi_mk_version(0, 3) && - sbi_probe_extension(SBI_EXT_PMU)) { - static_branch_enable(&riscv_pmu_sbi_available); - sbi_available = true; + if (sbi_probe_extension(SBI_EXT_PMU)) { + if (sbi_spec_version >= sbi_mk_version(0, 3)) { + static_branch_enable(&riscv_pmu_sbi_available); + sbi_available = true; + } + + if (sbi_spec_version >= sbi_mk_version(2, 0)) + sbi_v2_available = true; } - if (sbi_spec_version >= sbi_mk_version(2, 0)) - sbi_v2_available = true; /* * We need all three extensions to be present to access the counters * in S-mode via Supervisor Counter delegation.