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([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:37:14 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Subject: [RFC PATCH v1 07/10] riscv: Add RISC-V entries in processor type and ISA strings Date: Thu, 27 Feb 2025 18:06:25 +0530 Message-ID: <20250227123628.2931490-8-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250227_043715_913347_1332996D X-CRM114-Status: UNSURE ( 7.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: apatel@ventanamicro.com, cleger@rivosinc.com, tony.luck@intel.com, Himanshu Chauhan , robert.moore@intel.com, conor@kernel.org, james.morse@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, ardb@kernel.org, lenb@kernel.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org - Add RISCV in processor type - Add RISCV32/64 in ISA Signed-off-by: Himanshu Chauhan --- drivers/firmware/efi/cper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index b69e68ef3f02..f2908296a48f 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -110,6 +110,7 @@ static const char * const proc_type_strs[] = { "IA32/X64", "IA64", "ARM", + "RISCV", }; static const char * const proc_isa_strs[] = { @@ -118,6 +119,8 @@ static const char * const proc_isa_strs[] = { "X64", "ARM A32/T32", "ARM A64", + "RISCV32", + "RISCV64", }; const char * const cper_proc_error_type_strs[] = {