[03/13] riscv: Rename __switch_to_aux -> fpu

Message ID	28ce87a2bf6b73b01faa33b35df440effaab9a8b.1591344965.git.greentime.hu@sifive.com (mailing list archive)
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Headers	show Return-Path: <SRS0=MrGX=7Z=lists.infradead.org=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D15B2207D8 From: Greentime Hu <greentime.hu@sifive.com> To: greentime.hu@sifive.com, oleg@redhat.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/13] riscv: Rename __switch_to_aux -> fpu Date: Fri, 12 Jun 2020 15:09:52 +0800 Message-Id: <28ce87a2bf6b73b01faa33b35df440effaab9a8b.1591344965.git.greentime.hu@sifive.com> In-Reply-To: <cover.1591344965.git.greentime.hu@sifive.com> References: <cover.1591344965.git.greentime.hu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1041 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Precedence: list Cc: Anup Patel <anup@brainfault.org> Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [v6,00/13] riscv: Add vector ISA support [01/13] ptrace: Use regset_size() for dynamic regset [02/13] riscv: Separate patch for cflags and aflags [03/13] riscv: Rename __switch_to_aux -> fpu [04/13] riscv: Extending cpufeature.c to detect V-extension [05/13] riscv: Add new csr defines related to vector extension [06/13] riscv: Add vector feature to compile [07/13] riscv: Add has_vector/riscv_vsize to save vector features. [08/13] riscv: Reset vector register [09/13] riscv: Add vector struct and assembler definitions [10/13] riscv: Add task switch support for vector [11/13] riscv: Add ptrace vector support [12/13] riscv: Add sigcontext save/restore for vector [13/13] riscv: signal: Report signal frame size to userspace via auxv

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28ce87a2bf6b73b01faa33b35df440effaab9a8b.1591344965.git.greentime.hu@sifive.com (mailing list archive)

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DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D15B2207D8
From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, oleg@redhat.com, guoren@linux.alibaba.com,
 vincent.chen@sifive.com, paul.walmsley@sifive.com,
 palmerdabbelt@google.com, linux-riscv@lists.infradead.org,
 linux-kernel@vger.kernel.org
Subject: [PATCH 03/13] riscv: Rename __switch_to_aux -> fpu
Date: Fri, 12 Jun 2020 15:09:52 +0800
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 <28ce87a2bf6b73b01faa33b35df440effaab9a8b.1591344965.git.greentime.hu@sifive.com>
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Series

riscv: Add vector ISA support | expand

Commit Message

Greentime Hu June 12, 2020, 7:09 a.m. UTC

From: Guo Ren <guoren@linux.alibaba.com>

From: Guo Ren <ren_guo@c-sky.com>

The name of __switch_to_aux is not clear and rename it with the
determine function: __switch_to_fpu. Next we could add other regs'
switch.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/asm/switch_to.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 407bcc96a710..b9234e7178d0 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -44,7 +44,7 @@  static inline void fstate_restore(struct task_struct *task,
 	}
 }
 
-static inline void __switch_to_aux(struct task_struct *prev,
+static inline void __switch_to_fpu(struct task_struct *prev,
 				   struct task_struct *next)
 {
 	struct pt_regs *regs;
@@ -60,7 +60,7 @@  extern bool has_fpu;
 #define has_fpu false
 #define fstate_save(task, regs) do { } while (0)
 #define fstate_restore(task, regs) do { } while (0)
-#define __switch_to_aux(__prev, __next) do { } while (0)
+#define __switch_to_fpu(__prev, __next) do { } while (0)
 #endif
 
 extern struct task_struct *__switch_to(struct task_struct *,
@@ -71,7 +71,7 @@  do {							\
 	struct task_struct *__prev = (prev);		\
 	struct task_struct *__next = (next);		\
 	if (has_fpu)					\
-		__switch_to_aux(__prev, __next);	\
+		__switch_to_fpu(__prev, __next);	\
 	((last) = __switch_to(__prev, __next));		\
 } while (0)

[03/13] riscv: Rename __switch_to_aux -> fpu

Commit Message

Patch