| Message ID | 35c348437b6e18972ccaf90d9c38040caccd1f11.1706577450.git.unicorn_wang@outlook.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: sophgo: add reset support for SG2042 | expand |
>From: Chen Wang <unicorn_wang@outlook.com> > >Add reset generator node to device tree for SG2042. > LGTM Reviewed-by: Inochi Amaoto <inochiama@outlook.com> >Signed-off-by: Chen Wang <unicorn_wang@outlook.com> >--- > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > >diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi >index ead1cc35d88b..eeb341e16bfd 100644 >--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi >+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi >@@ -6,6 +6,8 @@ > /dts-v1/; > #include <dt-bindings/interrupt-controller/irq.h> > >+#include <dt-bindings/reset/sophgo,sg2042-reset.h> >+ > #include "sg2042-cpus.dtsi" > > / { >@@ -327,6 +329,12 @@ intc: interrupt-controller@7090000000 { > riscv,ndev = <224>; > }; > >+ rstgen: reset-controller@7030013000 { >+ compatible = "sophgo,sg2042-reset"; >+ reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; >+ #reset-cells = <1>; >+ }; >+ > uart0: serial@7040000000 { > compatible = "snps,dw-apb-uart"; > reg = <0x00000070 0x40000000 0x00000000 0x00001000>; >-- >2.25.1 > >
On Mon, 29 Jan 2024 17:49:45 PST (-0800), unicornxw@gmail.com wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++ > .../dt-bindings/reset/sophgo,sg2042-reset.h | 87 +++++++++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml > create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h > > diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml > new file mode 100644 > index 000000000000..76e1931f0908 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml > @@ -0,0 +1,35 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 SoC Reset Controller > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +properties: > + compatible: > + const: sophgo,sg2042-reset > + > + reg: > + maxItems: 1 > + > + "#reset-cells": > + const: 1 > + > +required: > + - compatible > + - reg > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + rstgen: reset-controller@c00 { > + compatible = "sophgo,sg2042-reset"; > + reg = <0xc00 0xc>; > + #reset-cells = <1>; > + }; > diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h > new file mode 100644 > index 000000000000..9ab0980625c1 > --- /dev/null > +++ b/include/dt-bindings/reset/sophgo,sg2042-reset.h > @@ -0,0 +1,87 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ > +/* > + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. > + */ > + > +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ > +#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ > + > +#define RST_MAIN_AP 0 > +#define RST_RISCV_CPU 1 > +#define RST_RISCV_LOW_SPEED_LOGIC 2 > +#define RST_RISCV_CMN 3 > +#define RST_HSDMA 4 > +#define RST_SYSDMA 5 > +#define RST_EFUSE0 6 > +#define RST_EFUSE1 7 > +#define RST_RTC 8 > +#define RST_TIMER 9 > +#define RST_WDT 10 > +#define RST_AHB_ROM0 11 > +#define RST_AHB_ROM1 12 > +#define RST_I2C0 13 > +#define RST_I2C1 14 > +#define RST_I2C2 15 > +#define RST_I2C3 16 > +#define RST_GPIO0 17 > +#define RST_GPIO1 18 > +#define RST_GPIO2 19 > +#define RST_PWM 20 > +#define RST_AXI_SRAM0 21 > +#define RST_AXI_SRAM1 22 > +#define RST_SF0 23 > +#define RST_SF1 24 > +#define RST_LPC 25 > +#define RST_ETH0 26 > +#define RST_EMMC 27 > +#define RST_SD 28 > +#define RST_UART0 29 > +#define RST_UART1 30 > +#define RST_UART2 31 > +#define RST_UART3 32 > +#define RST_SPI0 33 > +#define RST_SPI1 34 > +#define RST_DBG_I2C 35 > +#define RST_PCIE0 36 > +#define RST_PCIE1 37 > +#define RST_DDR0 38 > +#define RST_DDR1 39 > +#define RST_DDR2 40 > +#define RST_DDR3 41 > +#define RST_FAU0 42 > +#define RST_FAU1 43 > +#define RST_FAU2 44 > +#define RST_RXU0 45 > +#define RST_RXU1 46 > +#define RST_RXU2 47 > +#define RST_RXU3 48 > +#define RST_RXU4 49 > +#define RST_RXU5 50 > +#define RST_RXU6 51 > +#define RST_RXU7 52 > +#define RST_RXU8 53 > +#define RST_RXU9 54 > +#define RST_RXU10 55 > +#define RST_RXU11 56 > +#define RST_RXU12 57 > +#define RST_RXU13 58 > +#define RST_RXU14 59 > +#define RST_RXU15 60 > +#define RST_RXU16 61 > +#define RST_RXU17 62 > +#define RST_RXU18 63 > +#define RST_RXU19 64 > +#define RST_RXU20 65 > +#define RST_RXU21 66 > +#define RST_RXU22 67 > +#define RST_RXU23 68 > +#define RST_RXU24 69 > +#define RST_RXU25 70 > +#define RST_RXU26 71 > +#define RST_RXU27 72 > +#define RST_RXU28 73 > +#define RST_RXU29 74 > +#define RST_RXU30 75 > +#define RST_RXU31 76 > + > +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */ This is now Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo SG2042 SoC") which landed in Linus' tree. Looks like that went up via Inochi and Arnd. I don't have that in my for-next yet, so I'm just stashing away this patch for my tester. I'm happy to pick this up if folks want, but it'll probably be cleaner somewhere else.
On 2024/3/14 23:17, Palmer Dabbelt wrote: > On Mon, 29 Jan 2024 17:49:45 PST (-0800), unicornxw@gmail.com wrote: >> From: Chen Wang <unicorn_wang@outlook.com> >> >> Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC. >> >> [...] > > This is now > > Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo > SG2042 SoC") > > which landed in Linus' tree. Looks like that went up via Inochi and > Arnd. I don't have that in my for-next yet, so I'm just stashing away > this patch for my tester. > > I'm happy to pick this up if folks want, but it'll probably be cleaner > somewhere else. Hi, Palmer, I see Arnd has prepared a tag https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/tag/?h=soc-late-6.9 which contains the bindings part changes for sg2042 reset driver. Let's wait for Arnd to submit, although I haven't seen this in Linus's tree and not sure if Arnd have submitted this. Thanks, Chen
On Thu, 14 Mar 2024 17:15:11 PDT (-0700), unicorn_wang@outlook.com wrote: > > On 2024/3/14 23:17, Palmer Dabbelt wrote: >> On Mon, 29 Jan 2024 17:49:45 PST (-0800), unicornxw@gmail.com wrote: >>> From: Chen Wang <unicorn_wang@outlook.com> >>> >>> Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC. >>> >>> > [...] >> >> This is now >> >> Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo >> SG2042 SoC") >> >> which landed in Linus' tree. Looks like that went up via Inochi and >> Arnd. I don't have that in my for-next yet, so I'm just stashing away >> this patch for my tester. >> >> I'm happy to pick this up if folks want, but it'll probably be cleaner >> somewhere else. > > Hi, Palmer, > > I see Arnd has prepared a tag > https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/tag/?h=soc-late-6.9 > which contains the bindings part changes for sg2042 reset driver. > > Let's wait for Arnd to submit, although I haven't seen this in Linus's > tree and not sure if Arnd have submitted this. OK, sounds good. I realized I dropped the ball on a fix, so I'm not sending a PR this morning either way (I hadn't picked this up yet, though, so shouldn't make much of a difference). I'll just leave this in my not-for-next until it gets sorted out. Thanks! > > Thanks, > > Chen
On 2024/3/16 1:21, Palmer Dabbelt wrote: > [...] >>> >>> This is now >>> >>> Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo >>> SG2042 SoC") >>> >>> which landed in Linus' tree. Looks like that went up via Inochi and >>> Arnd. I don't have that in my for-next yet, so I'm just stashing away >>> this patch for my tester. >>> >>> I'm happy to pick this up if folks want, but it'll probably be cleaner >>> somewhere else. >> >> Hi, Palmer, >> >> I see Arnd has prepared a tag >> https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/tag/?h=soc-late-6.9 >> >> which contains the bindings part changes for sg2042 reset driver. >> >> Let's wait for Arnd to submit, although I haven't seen this in Linus's >> tree and not sure if Arnd have submitted this. > > OK, sounds good. I realized I dropped the ball on a fix, so I'm not > sending a PR this morning either way (I hadn't picked this up yet, > though, so shouldn't make much of a difference). > > I'll just leave this in my not-for-next until it gets sorted out. FYI, I see soc-late-6.9 has been on the master of Linus's tree. > > Thanks! > >> >> Thanks, >> >> Chen
diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml new file mode 100644 index 000000000000..76e1931f0908 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC Reset Controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +properties: + compatible: + const: sophgo,sg2042-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstgen: reset-controller@c00 { + compatible = "sophgo,sg2042-reset"; + reg = <0xc00 0xc>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h new file mode 100644 index 000000000000..9ab0980625c1 --- /dev/null +++ b/include/dt-bindings/reset/sophgo,sg2042-reset.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ +#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ + +#define RST_MAIN_AP 0 +#define RST_RISCV_CPU 1 +#define RST_RISCV_LOW_SPEED_LOGIC 2 +#define RST_RISCV_CMN 3 +#define RST_HSDMA 4 +#define RST_SYSDMA 5 +#define RST_EFUSE0 6 +#define RST_EFUSE1 7 +#define RST_RTC 8 +#define RST_TIMER 9 +#define RST_WDT 10 +#define RST_AHB_ROM0 11 +#define RST_AHB_ROM1 12 +#define RST_I2C0 13 +#define RST_I2C1 14 +#define RST_I2C2 15 +#define RST_I2C3 16 +#define RST_GPIO0 17 +#define RST_GPIO1 18 +#define RST_GPIO2 19 +#define RST_PWM 20 +#define RST_AXI_SRAM0 21 +#define RST_AXI_SRAM1 22 +#define RST_SF0 23 +#define RST_SF1 24 +#define RST_LPC 25 +#define RST_ETH0 26 +#define RST_EMMC 27 +#define RST_SD 28 +#define RST_UART0 29 +#define RST_UART1 30 +#define RST_UART2 31 +#define RST_UART3 32 +#define RST_SPI0 33 +#define RST_SPI1 34 +#define RST_DBG_I2C 35 +#define RST_PCIE0 36 +#define RST_PCIE1 37 +#define RST_DDR0 38 +#define RST_DDR1 39 +#define RST_DDR2 40 +#define RST_DDR3 41 +#define RST_FAU0 42 +#define RST_FAU1 43 +#define RST_FAU2 44 +#define RST_RXU0 45 +#define RST_RXU1 46 +#define RST_RXU2 47 +#define RST_RXU3 48 +#define RST_RXU4 49 +#define RST_RXU5 50 +#define RST_RXU6 51 +#define RST_RXU7 52 +#define RST_RXU8 53 +#define RST_RXU9 54 +#define RST_RXU10 55 +#define RST_RXU11 56 +#define RST_RXU12 57 +#define RST_RXU13 58 +#define RST_RXU14 59 +#define RST_RXU15 60 +#define RST_RXU16 61 +#define RST_RXU17 62 +#define RST_RXU18 63 +#define RST_RXU19 64 +#define RST_RXU20 65 +#define RST_RXU21 66 +#define RST_RXU22 67 +#define RST_RXU23 68 +#define RST_RXU24 69 +#define RST_RXU25 70 +#define RST_RXU26 71 +#define RST_RXU27 72 +#define RST_RXU28 73 +#define RST_RXU29 74 +#define RST_RXU30 75 +#define RST_RXU31 76 + +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */