| Message ID | 35ce2b9f7ca655eb3af13730b1ca9f05b518e08f.1690364259.git.haibo1.xu@intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISCV: Add kvm Sstc timer selftest | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 471aba2e4760 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, Jul 27, 2023 at 03:20:05PM +0800, Haibo Xu wrote: > Borrow some of the csr definitions and operations from kernel's > arch/riscv/include/asm/csr.h to tools/ for riscv. You should copy the entire file verbatim. Thanks, drew
On Fri, Jul 28, 2023 at 5:43 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Thu, Jul 27, 2023 at 03:20:05PM +0800, Haibo Xu wrote: > > Borrow some of the csr definitions and operations from kernel's > > arch/riscv/include/asm/csr.h to tools/ for riscv. > > You should copy the entire file verbatim. > Ok, will copy all the definitions in the original csr.h > Thanks, > drew
On Wed, Aug 02, 2023 at 10:05:00AM +0800, Haibo Xu wrote: > On Fri, Jul 28, 2023 at 5:43 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > > > On Thu, Jul 27, 2023 at 03:20:05PM +0800, Haibo Xu wrote: > > > Borrow some of the csr definitions and operations from kernel's > > > arch/riscv/include/asm/csr.h to tools/ for riscv. > > > > You should copy the entire file verbatim. > > > > Ok, will copy all the definitions in the original csr.h Why not include the original one? Maintain the one csr.h is more comfortable. > > > Thanks, > > drew >
On Wed, Aug 02, 2023 at 11:13:34PM -0400, Guo Ren wrote: > On Wed, Aug 02, 2023 at 10:05:00AM +0800, Haibo Xu wrote: > > On Fri, Jul 28, 2023 at 5:43 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > > > > > On Thu, Jul 27, 2023 at 03:20:05PM +0800, Haibo Xu wrote: > > > > Borrow some of the csr definitions and operations from kernel's > > > > arch/riscv/include/asm/csr.h to tools/ for riscv. > > > > > > You should copy the entire file verbatim. > > > > > > > Ok, will copy all the definitions in the original csr.h > Why not include the original one? Maintain the one csr.h is more > comfortable. selftests and other userspace tools can't always compile when including a kernel header without modifying the header in some way. Rather than polluting headers with #ifdeffery, the practice has been to copy necessary headers to tools/include and modify if necessary. Thanks, drew
On Thu, Aug 3, 2023 at 3:44 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Wed, Aug 02, 2023 at 11:13:34PM -0400, Guo Ren wrote: > > On Wed, Aug 02, 2023 at 10:05:00AM +0800, Haibo Xu wrote: > > > On Fri, Jul 28, 2023 at 5:43 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > > > > > > > On Thu, Jul 27, 2023 at 03:20:05PM +0800, Haibo Xu wrote: > > > > > Borrow some of the csr definitions and operations from kernel's > > > > > arch/riscv/include/asm/csr.h to tools/ for riscv. > > > > > > > > You should copy the entire file verbatim. > > > > > > > > > > Ok, will copy all the definitions in the original csr.h > > Why not include the original one? Maintain the one csr.h is more > > comfortable. > > selftests and other userspace tools can't always compile when including a > kernel header without modifying the header in some way. Rather than > polluting headers with #ifdeffery, the practice has been to copy necessary > headers to tools/include and modify if necessary. Okay, got it. > > Thanks, > drew
diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h new file mode 100644 index 000000000000..b437e6438216 --- /dev/null +++ b/tools/arch/riscv/include/asm/csr.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Regents of the University of California + * Copyright (c) 2023, Intel Corporation. + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) + +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ + +#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ +#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ +#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ + +/* Exception cause high bit - is an interrupt if set */ +#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) + +/* Interrupt causes (minus the high bit) */ +#define IRQ_S_SOFT 1 +#define IRQ_S_TIMER 5 +#define IRQ_S_EXT 9 + +/* Exception causes */ +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_INST_ILLEGAL 2 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_HYPERVISOR_SYSCALL 9 +#define EXC_SUPERVISOR_SYSCALL 10 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 +#define EXC_INST_GUEST_PAGE_FAULT 20 +#define EXC_LOAD_GUEST_PAGE_FAULT 21 +#define EXC_VIRTUAL_INST_FAULT 22 +#define EXC_STORE_GUEST_PAGE_FAULT 23 + +/* symbolic CSR names: */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 + +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 + +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + +/* IE/IP (Supervisor Interrupt Enable/Pending) flags */ +#define IE_SIE (_AC(0x1, UL) << IRQ_S_SOFT) +#define IE_TIE (_AC(0x1, UL) << IRQ_S_TIMER) +#define IE_EIE (_AC(0x1, UL) << IRQ_S_EXT) + +#ifndef __ASSEMBLY__ + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ + : "=r" (__v) : \ + : "memory"); \ + __v; \ +}) + +#define csr_write(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_CSR_H */
Borrow some of the csr definitions and operations from kernel's arch/riscv/include/asm/csr.h to tools/ for riscv. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> --- tools/arch/riscv/include/asm/csr.h | 127 +++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 tools/arch/riscv/include/asm/csr.h