[RFC,v8,16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally

Commit Message

Greentime Hu Sept. 8, 2021, 5:45 p.m. UTC

It may cause an illegal instruction exception if it doesn't use vsetvli
before vmv.v.i v0, 0.

Co-developed-by: Han-Kuan Chen <[e-mail]>
Signed-off-by: Han-Kuan Chen <[e-mail]>
Signed-off-by: Greentime Hu <[e-mail]>
---
 arch/riscv/kernel/head.S | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index cf331f138142..42eb3203fa77 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -442,6 +442,7 @@  ENTRY(reset_regs)
 
 	li	t1, SR_VS
 	csrs	CSR_STATUS, t1
+	vsetvli t1, x0, e8, m1
 	vmv.v.i v0, 0
 	vmv.v.i v1, 0
 	vmv.v.i v2, 0