[RFC,v8,07/21] riscv: Reset vector register

Message ID	6419a6326a5569987c4b3c5afb4b775887b2ca12.1631121222.git.greentime.hu@sifive.com (mailing list archive)
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Headers	show Return-Path: <SRS0=esFF=N6=lists.infradead.org=linux-riscv-bounces+linux-riscv=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0C33C6108B From: Greentime Hu <greentime.hu@sifive.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, vincent.chen@sifive.com Subject: [RFC PATCH v8 07/21] riscv: Reset vector register Date: Thu, 9 Sep 2021 01:45:19 +0800 Message-Id: <6419a6326a5569987c4b3c5afb4b775887b2ca12.1631121222.git.greentime.hu@sifive.com> In-Reply-To: <cover.1631121222.git.greentime.hu@sifive.com> References: <cover.1631121222.git.greentime.hu@sifive.com> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [RFC,v8,00/21] riscv: Add vector ISA support [RFC,v8,01/21] riscv: Separate patch for cflags and aflags [RFC,v8,02/21] riscv: Rename __switch_to_aux -> fpu [RFC,v8,03/21] riscv: Extending cpufeature.c to detect V-extension [RFC,v8,04/21] riscv: Add new csr defines related to vector extension [RFC,v8,05/21] riscv: Add vector feature to compile [RFC,v8,06/21] riscv: Add has_vector/riscv_vsize to save vector features. [RFC,v8,07/21] riscv: Reset vector register [RFC,v8,08/21] riscv: Add vector struct and assembler definitions [RFC,v8,09/21] riscv: Add task switch support for vector [RFC,v8,10/21] riscv: Add ptrace vector support [RFC,v8,11/21] riscv: Add sigcontext save/restore for vector [RFC,v8,12/21] riscv: signal: Report signal frame size to userspace via auxv [RFC,v8,13/21] riscv: Add support for kernel mode vector [RFC,v8,14/21] riscv: Use CSR_STATUS to replace sstatus in vector.S [RFC,v8,15/21] riscv: Add vector extension XOR implementation [RFC,v8,16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally [RFC,v8,17/21] riscv: Optimize vector registers initialization [RFC,v8,18/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vect… [RFC,v8,19/21] riscv: Allocate space for vector registers in start_thread() [RFC,v8,20/21] riscv: Optimize task switch codes of vector [RFC,v8,21/21] riscv: Turn has_vector into a static key if VECTOR=y

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6419a6326a5569987c4b3c5afb4b775887b2ca12.1631121222.git.greentime.hu@sifive.com (mailing list archive)

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DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0C33C6108B
From: Greentime Hu <greentime.hu@sifive.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
 aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com,
 vincent.chen@sifive.com
Subject: [RFC PATCH v8 07/21] riscv: Reset vector register
Date: Thu,  9 Sep 2021 01:45:19 +0800
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Series

riscv: Add vector ISA support | expand

Commit Message

Greentime Hu Sept. 8, 2021, 5:45 p.m. UTC

From: Guo Ren <guoren@linux.alibaba.com>

Reset vector registers at boot-time and disable vector instructions
execution for kernel mode.

[greentime.hu@sifive.com: add comments]
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/kernel/entry.S |  6 ++---
 arch/riscv/kernel/head.S  | 49 +++++++++++++++++++++++++++++++++++++--
 2 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 98f502654edd..ad0fa80ada81 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -77,10 +77,10 @@  _save_context:
 	 * Disable user-mode memory access as it should only be set in the
 	 * actual user copy routines.
 	 *
-	 * Disable the FPU to detect illegal usage of floating point in kernel
-	 * space.
+	 * Disable the FPU/Vector to detect illegal usage of floating point
+	 * or vector in kernel space.
 	 */
-	li t0, SR_SUM | SR_FS
+	li t0, SR_SUM | SR_FS | SR_VS
 
 	REG_L s0, TASK_TI_USER_SP(tp)
 	csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index fce5184b22c3..cf331f138142 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -241,10 +241,10 @@  pmp_done:
 .option pop
 
 	/*
-	 * Disable FPU to detect illegal usage of
+	 * Disable FPU & VECTOR to detect illegal usage of
 	 * floating point in kernel space
 	 */
-	li t0, SR_FS
+	li t0, SR_FS | SR_VS
 	csrc CSR_STATUS, t0
 
 #ifdef CONFIG_SMP
@@ -432,6 +432,51 @@  ENTRY(reset_regs)
 	csrw	fcsr, 0
 	/* note that the caller must clear SR_FS */
 #endif /* CONFIG_FPU */
+
+#ifdef CONFIG_VECTOR
+	csrr	t0, CSR_MISA
+	li	t1, (COMPAT_HWCAP_ISA_V >> 16)
+	slli	t1, t1, 16
+	and	t0, t0, t1
+	beqz	t0, .Lreset_regs_done
+
+	li	t1, SR_VS
+	csrs	CSR_STATUS, t1
+	vmv.v.i v0, 0
+	vmv.v.i v1, 0
+	vmv.v.i v2, 0
+	vmv.v.i v3, 0
+	vmv.v.i v4, 0
+	vmv.v.i v5, 0
+	vmv.v.i v6, 0
+	vmv.v.i v7, 0
+	vmv.v.i v8, 0
+	vmv.v.i v9, 0
+	vmv.v.i v10, 0
+	vmv.v.i v11, 0
+	vmv.v.i v12, 0
+	vmv.v.i v13, 0
+	vmv.v.i v14, 0
+	vmv.v.i v15, 0
+	vmv.v.i v16, 0
+	vmv.v.i v17, 0
+	vmv.v.i v18, 0
+	vmv.v.i v19, 0
+	vmv.v.i v20, 0
+	vmv.v.i v21, 0
+	vmv.v.i v22, 0
+	vmv.v.i v23, 0
+	vmv.v.i v24, 0
+	vmv.v.i v25, 0
+	vmv.v.i v26, 0
+	vmv.v.i v27, 0
+	vmv.v.i v28, 0
+	vmv.v.i v29, 0
+	vmv.v.i v30, 0
+	vmv.v.i v31, 0
+	/* note that the caller must clear SR_VS */
+#endif /* CONFIG_VECTOR */
+
 .Lreset_regs_done:
 	ret
 END(reset_regs)

[RFC,v8,07/21] riscv: Reset vector register

Commit Message

Patch