[v2,2/3] riscv: dts: starfive: jh7110: Add sys-syscon property to usbphy0

Commit Message

Jan Kiszka Aug. 12, 2024, 2:15 p.m. UTC

From: Jan Kiszka <[e-mail]>

Allows the PHY to connect to its USB controller.

Signed-off-by: Jan Kiszka <[e-mail]>
---
CC: Rob Herring <[e-mail]>
CC: Krzysztof Kozlowski <[e-mail]>
CC: Conor Dooley <[e-mail]>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0d8339357bad..0c0b66a69065 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -606,6 +606,7 @@  usbphy0: phy@10200000 {
 				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 			clock-names = "125m", "app_125m";
 			#phy-cells = <0>;
+			starfive,sys-syscon = <&sys_syscon 0x18>;
 		};
 
 		pciephy0: phy@10210000 {