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[1/2] RISC-V: make ISA string workaround case-insensitive

Message ID 74ef735a676c3f21cbd8c2ee19d4a577a920f23e.1690006695.git.research_trasio@irq.a4lg.com (mailing list archive)
State Handled Elsewhere
Headers show
Series RISC-V: minor fixes to the QEMU workaround in ISA string parser | expand

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conchuod/fixes_present success Fixes tag not required for -next series
conchuod/maintainers_pattern success MAINTAINERS pattern errors before the patch: 4 and now 4
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conchuod/kdoc success Errors and warnings before: 0 this patch: 0
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conchuod/build_rv64_gcc_allmodconfig success Errors and warnings before: 9 this patch: 9
conchuod/build_rv32_defconfig success Build OK
conchuod/dtb_warn_rv64 success Errors and warnings before: 3 this patch: 3
conchuod/header_inline success No static functions without inline keyword in header files
conchuod/checkpatch success total: 0 errors, 0 warnings, 0 checks, 21 lines checked
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conchuod/verify_fixes success No Fixes tag
conchuod/build_rv64_nommu_virt_defconfig success Build OK

Commit Message

Tsukasa OI July 22, 2023, 6:22 a.m. UTC 
From: Tsukasa OI <research_trasio@irq.a4lg.com>

This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
ISA string parsing").

Although the QEMU workaround in the ISA string parser works well with
lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
case-sensitive handling in the case-insensitive parser can be confusing.

This commit makes the QEMU workaround case-insensitive and gives more
robustness (against manually crafted Device Tree blobs) and less confusion
to kernel developers.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Conor Dooley July 22, 2023, 10:49 a.m. UTC | #1 
On Sat, Jul 22, 2023 at 06:22:37AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
> ISA string parsing").
> 
> Although the QEMU workaround in the ISA string parser works well with
> lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
> case-sensitive handling in the case-insensitive parser can be confusing.

> This commit makes the QEMU workaround case-insensitive and gives more
> robustness (against manually crafted Device Tree blobs) and less confusion
> to kernel developers.

If people are manually crafting their DT, they should check it for
compliance with dt-validate (or dtbs_check). The case insensitivity only
makes sense for ACPI, but by the time ACPI was supported, you'd already
removed the "su" stuff from QEMU.

Thanks,
Conor.

> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index a8f66c015229..63277cdc1ea5 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -168,19 +168,19 @@ void __init riscv_fill_hwcap(void)
>  
>  			switch (*ext) {
>  			case 's':
> +			case 'S':
>  				/*
>  				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
>  				 * No need to set the bit in riscv_isa as 's' & 'u' are
>  				 * not valid ISA extensions. It works until multi-letter
>  				 * extension starting with "Su" appears.
>  				 */
> -				if (ext[-1] != '_' && ext[1] == 'u') {
> +				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
>  					++isa;
>  					ext_err = true;
>  					break;
>  				}
>  				fallthrough;
> -			case 'S':
>  			case 'x':
>  			case 'X':
>  			case 'z':
> -- 
> 2.40.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
diff mbox series

Patch

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a8f66c015229..63277cdc1ea5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -168,19 +168,19 @@  void __init riscv_fill_hwcap(void)
 
 			switch (*ext) {
 			case 's':
+			case 'S':
 				/*
 				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
 				 * No need to set the bit in riscv_isa as 's' & 'u' are
 				 * not valid ISA extensions. It works until multi-letter
 				 * extension starting with "Su" appears.
 				 */
-				if (ext[-1] != '_' && ext[1] == 'u') {
+				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
 					++isa;
 					ext_err = true;
 					break;
 				}
 				fallthrough;
-			case 'S':
 			case 'x':
 			case 'X':
 			case 'z':