[06/17] riscv: Reset vector register

Message ID	CAM2SziUSPkCf+GCVQu5k_H6TzUD117zCVe=Tyqv1DuwUq-Ls3g@mail.gmail.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> MIME-Version: 1.0 From: Chris Stillson <stillson@rivosinc.com> Date: Wed, 21 Sep 2022 09:47:43 -0700 Message-ID: <CAM2SziUSPkCf+GCVQu5k_H6TzUD117zCVe=Tyqv1DuwUq-Ls3g@mail.gmail.com> Subject: [PATCH 06/17] riscv: Reset vector register To: linux-riscv@lists.infradead.org Cc: palmer@dabbelt.com Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Prctl to enable vector commands, previous vector patches rebased \| expand [00/17] Prctl to enable vector commands, previous vector patches rebased [01/17] riscv: Rename __switch_to_aux -> fpu [02/17] riscv: Extending cpufeature.c to detect V-extension [03/17] riscv: Add new csr defines related to vector extension [04/17] riscv: Add vector feature to compile [05/17] riscv: Add has_vector/riscv_vsize to save vector features. [06/17] riscv: Reset vector register [07/17] riscv: Add vector struct and assembler definitions [08/17] riscv: Add task switch support for vector [09/17] riscv: Add ptrace vector support [10/17] riscv: Add sigcontext save/restore for vector [11/17] riscv: signal: Report signal frame size to userspace via auxv [12/17] riscv: Add support for kernel mode vector [13/17] riscv: Add vector extension XOR implementation [14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux [15/17] riscv: Add V extension to KVM ISA allow list [16/17] riscv: KVM: Add vector lazy save/restore support [17/17] riscv: prctl to enable vector commands

Message ID

CAM2SziUSPkCf+GCVQu5k_H6TzUD117zCVe=Tyqv1DuwUq-Ls3g@mail.gmail.com (mailing list archive)

State

Superseded

Headers

MIME-Version: 1.0
From: Chris Stillson <stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 09:47:43 -0700
Message-ID: 
 <CAM2SziUSPkCf+GCVQu5k_H6TzUD117zCVe=Tyqv1DuwUq-Ls3g@mail.gmail.com>
Subject: [PATCH 06/17] riscv: Reset vector register
To: linux-riscv@lists.infradead.org
Cc: palmer@dabbelt.com
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 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

Prctl to enable vector commands, previous vector patches rebased | expand

Commit Message

Chris Stillson Sept. 21, 2022, 4:47 p.m. UTC

Reset vector registers at boot-time and disable vector instructions
execution for kernel mode.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/kernel/entry.S |  6 +++---
 arch/riscv/kernel/head.S  | 35 +++++++++++++++++++++++++++++------
 2 files changed, 32 insertions(+), 9 deletions(-)

--
2.25.1

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index b9eda3fcbd6d..1e9987376591 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -77,10 +77,10 @@  _save_context:
         * Disable user-mode memory access as it should only be set in the
         * actual user copy routines.
         *
-        * Disable the FPU to detect illegal usage of floating point in kernel
-        * space.
+        * Disable the FPU/Vector to detect illegal usage of floating point
+        * or vector in kernel space.
         */
-       li t0, SR_SUM | SR_FS
+       li t0, SR_SUM | SR_FS | SR_VS

        REG_L s0, TASK_TI_USER_SP(tp)
        csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index b865046e4dbb..2c81ca42ec4e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -140,10 +140,10 @@  secondary_start_sbi:
        .option pop

        /*
-        * Disable FPU to detect illegal usage of
-        * floating point in kernel space
+        * Disable FPU & VECTOR to detect illegal usage of
+        * floating point or vector in kernel space
         */
-       li t0, SR_FS
+       li t0, SR_FS | SR_VS
        csrc CSR_STATUS, t0

        /* Set trap vector to spin forever to help debug */
@@ -234,10 +234,10 @@  pmp_done:
 .option pop

        /*
-        * Disable FPU to detect illegal usage of
-        * floating point in kernel space
+        * Disable FPU & VECTOR to detect illegal usage of
+        * floating point or vector in kernel space
         */
-       li t0, SR_FS
+       li t0, SR_FS | SR_VS
        csrc CSR_STATUS, t0

 #ifdef CONFIG_RISCV_BOOT_SPINWAIT
@@ -431,6 +431,29 @@  ENTRY(reset_regs)
        csrw    fcsr, 0
        /* note that the caller must clear SR_FS */
 #endif /* CONFIG_FPU */
+
+#ifdef CONFIG_VECTOR
+       csrr    t0, CSR_MISA
+       li      t1, COMPAT_HWCAP_ISA_V
+       and     t0, t0, t1
+       beqz    t0, .Lreset_regs_done
+
+       /*
+        * Clear vector registers and reset vcsr
+        * VLMAX has a defined value, VLEN is a constant,
+        * and this form of vsetvli is defined to set vl to VLMAX.
+        */
+       li      t1, SR_VS
+       csrs    CSR_STATUS, t1
+       csrs    CSR_VCSR, x0
+       vsetvli t1, x0, e8, m8, ta, ma
+       vmv.v.i v0, 0
+       vmv.v.i v8, 0
+       vmv.v.i v16, 0
+       vmv.v.i v24, 0
+       /* note that the caller must clear SR_VS */
+#endif /* CONFIG_VECTOR */
+
 .Lreset_regs_done:
        ret
 END(reset_regs)

[06/17] riscv: Reset vector register

Commit Message

Patch