[07/17] riscv: Add vector struct and assembler definitions

Message ID	CAM2SziWHRo6wY5FNeNZ+V8q73LdEvv1VA8CRRzNR6rfLDPLZew@mail.gmail.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> MIME-Version: 1.0 From: Chris Stillson <stillson@rivosinc.com> Date: Wed, 21 Sep 2022 09:48:04 -0700 Message-ID: <CAM2SziWHRo6wY5FNeNZ+V8q73LdEvv1VA8CRRzNR6rfLDPLZew@mail.gmail.com> Subject: [PATCH 07/17] riscv: Add vector struct and assembler definitions To: linux-riscv@lists.infradead.org Cc: palmer@dabbelt.com Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Prctl to enable vector commands, previous vector patches rebased \| expand [00/17] Prctl to enable vector commands, previous vector patches rebased [01/17] riscv: Rename __switch_to_aux -> fpu [02/17] riscv: Extending cpufeature.c to detect V-extension [03/17] riscv: Add new csr defines related to vector extension [04/17] riscv: Add vector feature to compile [05/17] riscv: Add has_vector/riscv_vsize to save vector features. [06/17] riscv: Reset vector register [07/17] riscv: Add vector struct and assembler definitions [08/17] riscv: Add task switch support for vector [09/17] riscv: Add ptrace vector support [10/17] riscv: Add sigcontext save/restore for vector [11/17] riscv: signal: Report signal frame size to userspace via auxv [12/17] riscv: Add support for kernel mode vector [13/17] riscv: Add vector extension XOR implementation [14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux [15/17] riscv: Add V extension to KVM ISA allow list [16/17] riscv: KVM: Add vector lazy save/restore support [17/17] riscv: prctl to enable vector commands

Message ID

CAM2SziWHRo6wY5FNeNZ+V8q73LdEvv1VA8CRRzNR6rfLDPLZew@mail.gmail.com (mailing list archive)

State

Superseded

Headers

MIME-Version: 1.0
From: Chris Stillson <stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 09:48:04 -0700
Message-ID: 
 <CAM2SziWHRo6wY5FNeNZ+V8q73LdEvv1VA8CRRzNR6rfLDPLZew@mail.gmail.com>
Subject: [PATCH 07/17] riscv: Add vector struct and assembler definitions
To: linux-riscv@lists.infradead.org
Cc: palmer@dabbelt.com
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Series

Prctl to enable vector commands, previous vector patches rebased | expand

Commit Message

Chris Stillson Sept. 21, 2022, 4:48 p.m. UTC

Add vector state context struct in struct thread and asm-offsets.c
definitions.

The vector registers will be saved in datap pointer of __riscv_v_state. It
will be dynamically allocated in kernel space. It will be put right after
the __riscv_v_state data structure in user space.

Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/include/asm/processor.h   |  1 +
 arch/riscv/include/uapi/asm/ptrace.h | 17 +++++++++++++++++
 arch/riscv/kernel/asm-offsets.c      |  6 ++++++
 3 files changed, 24 insertions(+)

--
2.25.1

diff --git a/arch/riscv/include/asm/processor.h
b/arch/riscv/include/asm/processor.h
index 19eedd4af4cd..95917a2b24f9 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -39,6 +39,7 @@  struct thread_struct {
        unsigned long s[12];    /* s[0]: frame pointer */
        struct __riscv_d_ext_state fstate;
        unsigned long bad_cause;
+       struct __riscv_v_state vstate;
 };

 /* Whitelist the fstate from the task_struct for hardened usercopy */
diff --git a/arch/riscv/include/uapi/asm/ptrace.h
b/arch/riscv/include/uapi/asm/ptrace.h
index 882547f6bd5c..6ee1ca2edfa7 100644
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -77,6 +77,23 @@  union __riscv_fp_state {
        struct __riscv_q_ext_state q;
 };

+struct __riscv_v_state {
+       unsigned long vstart;
+       unsigned long vl;
+       unsigned long vtype;
+       unsigned long vcsr;
+       void *datap;
+       /*
+        * In signal handler, datap will be set a correct user stack offset
+        * and vector registers will be copied to the address of datap
+        * pointer.
+        *
+        * In ptrace syscall, datap will be set to zero and the vector
+        * registers will be copied to the address right after this
+        * structure.
+        */
+};
+
 #endif /* __ASSEMBLY__ */

 #endif /* _UAPI_ASM_RISCV_PTRACE_H */
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index df9444397908..37e3e6a8d877 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -75,6 +75,12 @@  void asm_offsets(void)
        OFFSET(TSK_STACK_CANARY, task_struct, stack_canary);
 #endif

+       OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart);
+       OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl);
+       OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype);
+       OFFSET(RISCV_V_STATE_VCSR, __riscv_v_state, vcsr);
+       OFFSET(RISCV_V_STATE_DATAP, __riscv_v_state, datap);
+
        DEFINE(PT_SIZE, sizeof(struct pt_regs));
        OFFSET(PT_EPC, pt_regs, epc);
        OFFSET(PT_RA, pt_regs, ra);

[07/17] riscv: Add vector struct and assembler definitions

Commit Message

Patch