| Message ID | DM6PR20MB23167ABF18C1F004A5710D4FAB7A2@DM6PR20MB2316.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | [v2] riscv: dts: sophgo: add timer dt node for CV1800 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Thu, Jan 25, 2024 at 05:46:23PM +0800, AnnanLiu wrote: > Add the timer device tree node to CV1800 SoC. > > Signed-off-by: AnnanLiu <annan.liu.xdu@outlook.com> > --- > This patch depends on the clk driver and reset driver. > Clk driver link: > https://lore.kernel.org/all/IA1PR20MB49539CDAD9A268CBF6CA184BBB9FA@IA1PR20MB4953.namprd20.prod.outlook.com/ > Reset driver link: > https://lore.kernel.org/all/20231113005503.2423-1-jszhang@kernel.org/ > > Changes since v1: > - Change the status of the timer from disabled to okay. > v1 link: > https://lore.kernel.org/all/DM6PR20MB23167E08FCA546D6C1899CB1AB9EA@DM6PR20MB2316.namprd20.prod.outlook.com/ > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 73 +++++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index aec6401a467b..aef7970af2b8 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > /* > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2024 Annan Liu <annan.liu.xdu@outlook.com> > */ > > #include <dt-bindings/interrupt-controller/irq.h> > @@ -113,6 +114,78 @@ plic: interrupt-controller@70000000 { > riscv,ndev = <101>; > }; > > + timer0: timer@030a0000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x030a0000 0x14>; > + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + resets = <&rst RST_TIMER0>; > + status = "okay"; Do these really have no interface clock? I'd expect something that is almost certainly sitting on a apb (or similar) interface to have one. Thanks, Conor.
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index aec6401a467b..aef7970af2b8 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2024 Annan Liu <annan.liu.xdu@outlook.com> */ #include <dt-bindings/interrupt-controller/irq.h> @@ -113,6 +114,78 @@ plic: interrupt-controller@70000000 { riscv,ndev = <101>; }; + timer0: timer@030a0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0000 0x14>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER0>; + status = "okay"; + }; + + timer1: timer@030a0014 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0014 0x14>; + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@030a0028 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0028 0x14>; + interrupts = <81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER2>; + status = "disabled"; + }; + + timer3: timer@030a003c { + compatible = "snps,dw-apb-timer"; + reg = <0x030a003c 0x14>; + interrupts = <82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER3>; + status = "disabled"; + }; + + timer4: timer@030a0050 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0050 0x14>; + interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER4>; + status = "disabled"; + }; + + timer5: timer@30a0064 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0064 0x14>; + interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER5>; + status = "disabled"; + }; + + timer6: timer@030a0078 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0078 0x14>; + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER6>; + status = "disabled"; + }; + + timer7: timer@030a008c { + compatible = "snps,dw-apb-timer"; + reg = <0x030a008c 0x14>; + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER7>; + status = "disabled"; + }; + clint: timer@74000000 { compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; reg = <0x74000000 0x10000>;
Add the timer device tree node to CV1800 SoC. Signed-off-by: AnnanLiu <annan.liu.xdu@outlook.com> --- This patch depends on the clk driver and reset driver. Clk driver link: https://lore.kernel.org/all/IA1PR20MB49539CDAD9A268CBF6CA184BBB9FA@IA1PR20MB4953.namprd20.prod.outlook.com/ Reset driver link: https://lore.kernel.org/all/20231113005503.2423-1-jszhang@kernel.org/ Changes since v1: - Change the status of the timer from disabled to okay. v1 link: https://lore.kernel.org/all/DM6PR20MB23167E08FCA546D6C1899CB1AB9EA@DM6PR20MB2316.namprd20.prod.outlook.com/ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 73 +++++++++++++++++++++++++ 1 file changed, 73 insertions(+)