| Message ID | IA1PR20MB49531F6DFD2F116207C1397DBBB72@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | riscv: dts: sophgo: Add i2c device support for sg2042 | expand |
On 2024/7/29 10:13, Inochi Amaoto wrote: > As all peripherals of sg2042 share the same "interrupt-parent", > there is no need to use peripherals specific "interrupt-parent". > Define "interrupt-parent" in the SoC level. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> > --- > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > index 34c802bd3f9b..c61d8061119d 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -44,6 +44,7 @@ soc: soc { > compatible = "simple-bus"; > #address-cells = <2>; > #size-cells = <2>; > + interrupt-parent = <&intc>; > ranges; > > pllclk: clock-controller@70300100c0 { > @@ -388,7 +389,6 @@ rstgen: reset-controller@7030013000 { > uart0: serial@7040000000 { > compatible = "snps,dw-apb-uart"; > reg = <0x00000070 0x40000000 0x00000000 0x00001000>; > - interrupt-parent = <&intc>; > interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; > clock-frequency = <500000000>; > clocks = <&clkgen GATE_CLK_UART_500M>, > -- > 2.45.2 >
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 34c802bd3f9b..c61d8061119d 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -44,6 +44,7 @@ soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&intc>; ranges; pllclk: clock-controller@70300100c0 { @@ -388,7 +389,6 @@ rstgen: reset-controller@7030013000 { uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; - interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; clocks = <&clkgen GATE_CLK_UART_500M>,
As all peripherals of sg2042 share the same "interrupt-parent", there is no need to use peripherals specific "interrupt-parent". Define "interrupt-parent" in the SoC level. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.45.2