| Message ID | IA1PR20MB49534918FCA69399CE2E0C53BBE0A@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | [v4] riscv: dts: allwinner: d1: Add PMU event node | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 9f944d2e0ab3 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 12 this patch: 12 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 43 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote: > D1 has several pmu events supported by opensbi. > These events can be used by perf for profiling. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf > Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 > --- > changed from v3: > 1. remove wrong event mapping of 0x0000a > 2. add reference url of c906 events implementation (D1 only support events > described in R1S0 user manual, but event mapping is the same) Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT. Acked-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > > changed from v2: > 1. move pmu node from /soc to / to avoid warnings when checking. > > The meaning of T-HEAD events can be found in this pending patch: > https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com > > The patch above also provides a example that shows how to setup > environment and use perf with T-HEAD events. > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 8275630af977..53a984d78e3f 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 { > #interrupt-cells = <2>; > }; > }; > + > + pmu { > + compatible = "riscv,pmu"; > + riscv,event-to-mhpmcounters = > + <0x00003 0x00003 0x00000008>, > + <0x00004 0x00004 0x00000010>, > + <0x00005 0x00005 0x00000200>, > + <0x00006 0x00006 0x00000100>, > + <0x10000 0x10000 0x00004000>, > + <0x10001 0x10001 0x00008000>, > + <0x10002 0x10002 0x00010000>, > + <0x10003 0x10003 0x00020000>, > + <0x10019 0x10019 0x00000040>, > + <0x10021 0x10021 0x00000020>; > + riscv,event-to-mhpmevent = > + <0x00003 0x00000000 0x00000001>, > + <0x00004 0x00000000 0x00000002>, > + <0x00005 0x00000000 0x00000007>, > + <0x00006 0x00000000 0x00000006>, > + <0x10000 0x00000000 0x0000000c>, > + <0x10001 0x00000000 0x0000000d>, > + <0x10002 0x00000000 0x0000000e>, > + <0x10003 0x00000000 0x0000000f>, > + <0x10019 0x00000000 0x00000004>, > + <0x10021 0x00000000 0x00000003>; > + riscv,raw-event-to-mhpmcounters = > + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, > + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, > + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, > + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, > + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, > + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, > + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, > + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, > + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, > + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, > + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > + }; > }; > -- > 2.42.0 >
>On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote: >> D1 has several pmu events supported by opensbi. >> These events can be used by perf for profiling. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf >> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 >> --- >> changed from v3: >> 1. remove wrong event mapping of 0x0000a >> 2. add reference url of c906 events implementation (D1 only support events >> described in R1S0 user manual, but event mapping is the same) > >Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT. >Acked-by: Conor Dooley <conor.dooley@microchip.com> > >Thanks, >Conor. Sorry for this, I am not sure whether to preserve the ack. Thank you for your ack again, and I will reserve this if no big change happens.
On 28/08/2023 08:41, Inochi Amaoto wrote: >> On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote: >>> D1 has several pmu events supported by opensbi. >>> These events can be used by perf for profiling. >>> >>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf >>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 >>> --- >>> changed from v3: >>> 1. remove wrong event mapping of 0x0000a >>> 2. add reference url of c906 events implementation (D1 only support events >>> described in R1S0 user manual, but event mapping is the same) >> >> Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT. >> Acked-by: Conor Dooley <conor.dooley@microchip.com> >> >> Thanks, >> Conor. > > Sorry for this, I am not sure whether to preserve the ack. > Thank you for your ack again, and I will reserve this if no big change > happens. https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577 Best regards, Krzysztof
>On 28/08/2023 08:41, Inochi Amaoto wrote: >>> On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote: >>>> D1 has several pmu events supported by opensbi. >>>> These events can be used by perf for profiling. >>>> >>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >>>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf >>>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 >>>> --- >>>> changed from v3: >>>> 1. remove wrong event mapping of 0x0000a >>>> 2. add reference url of c906 events implementation (D1 only support events >>>> described in R1S0 user manual, but event mapping is the same) >>> >>> Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT. >>> Acked-by: Conor Dooley <conor.dooley@microchip.com> >>> >>> Thanks, >>> Conor. >> >> Sorry for this, I am not sure whether to preserve the ack. >> Thank you for your ack again, and I will reserve this if no big change >> happens. > >https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577 > >Best regards, >Krzysztof > Thanks. I will take care of this.
On Monday, August 28, 2023 6:30:22 AM CEST Inochi Amaoto wrote: > D1 has several pmu events supported by opensbi. > These events can be used by perf for profiling. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf > Link: > https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/ > pmu/rtl/aq_hpcp_top.v#L657 Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> What's the status of dependencies? Are they merged? Best regards, Jernej > --- > changed from v3: > 1. remove wrong event mapping of 0x0000a > 2. add reference url of c906 events implementation (D1 only support events > described in R1S0 user manual, but event mapping is the same) > > changed from v2: > 1. move pmu node from /soc to / to avoid warnings when checking. > > The meaning of T-HEAD events can be found in this pending patch: > https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BB > E2A@IA1PR20MB4953.namprd20.prod.outlook.com > > The patch above also provides a example that shows how to setup > environment and use perf with T-HEAD events. > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index > 8275630af977..53a984d78e3f 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 { > #interrupt-cells = <2>; > }; > }; > + > + pmu { > + compatible = "riscv,pmu"; > + riscv,event-to-mhpmcounters = > + <0x00003 0x00003 0x00000008>, > + <0x00004 0x00004 0x00000010>, > + <0x00005 0x00005 0x00000200>, > + <0x00006 0x00006 0x00000100>, > + <0x10000 0x10000 0x00004000>, > + <0x10001 0x10001 0x00008000>, > + <0x10002 0x10002 0x00010000>, > + <0x10003 0x10003 0x00020000>, > + <0x10019 0x10019 0x00000040>, > + <0x10021 0x10021 0x00000020>; > + riscv,event-to-mhpmevent = > + <0x00003 0x00000000 0x00000001>, > + <0x00004 0x00000000 0x00000002>, > + <0x00005 0x00000000 0x00000007>, > + <0x00006 0x00000000 0x00000006>, > + <0x10000 0x00000000 0x0000000c>, > + <0x10001 0x00000000 0x0000000d>, > + <0x10002 0x00000000 0x0000000e>, > + <0x10003 0x00000000 0x0000000f>, > + <0x10019 0x00000000 0x00000004>, > + <0x10021 0x00000000 0x00000003>; > + riscv,raw-event-to-mhpmcounters = > + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, > + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, > + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, > + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, > + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, > + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, > + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, > + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, > + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, > + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, > + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > + }; > }; > -- > 2.42.0
On Mon, Aug 28, 2023 at 12:29 PM Inochi Amaoto <inochiama@outlook.com> wrote: > > D1 has several pmu events supported by opensbi. > These events can be used by perf for profiling. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf > Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 > --- > changed from v3: > 1. remove wrong event mapping of 0x0000a > 2. add reference url of c906 events implementation (D1 only support events > described in R1S0 user manual, but event mapping is the same) > > changed from v2: > 1. move pmu node from /soc to / to avoid warnings when checking. > > The meaning of T-HEAD events can be found in this pending patch: > https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com > > The patch above also provides a example that shows how to setup > environment and use perf with T-HEAD events. > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 8275630af977..53a984d78e3f 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 { > #interrupt-cells = <2>; > }; > }; > + > + pmu { > + compatible = "riscv,pmu"; > + riscv,event-to-mhpmcounters = > + <0x00003 0x00003 0x00000008>, > + <0x00004 0x00004 0x00000010>, > + <0x00005 0x00005 0x00000200>, > + <0x00006 0x00006 0x00000100>, > + <0x10000 0x10000 0x00004000>, > + <0x10001 0x10001 0x00008000>, > + <0x10002 0x10002 0x00010000>, > + <0x10003 0x10003 0x00020000>, > + <0x10019 0x10019 0x00000040>, > + <0x10021 0x10021 0x00000020>; > + riscv,event-to-mhpmevent = > + <0x00003 0x00000000 0x00000001>, > + <0x00004 0x00000000 0x00000002>, > + <0x00005 0x00000000 0x00000007>, > + <0x00006 0x00000000 0x00000006>, > + <0x10000 0x00000000 0x0000000c>, > + <0x10001 0x00000000 0x0000000d>, > + <0x10002 0x00000000 0x0000000e>, > + <0x10003 0x00000000 0x0000000f>, > + <0x10019 0x00000000 0x00000004>, > + <0x10021 0x00000000 0x00000003>; > + riscv,raw-event-to-mhpmcounters = > + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, > + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, > + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, > + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, > + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, > + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, > + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, > + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, > + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, > + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, > + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > + }; > }; > -- > 2.42.0 > Reviewed-by: Guo Ren <guoren@kernel.org>
Dne ponedeljek, 28. avgust 2023 ob 06:30:22 CEST je Inochi Amaoto napisal(a): > D1 has several pmu events supported by opensbi. > These events can be used by perf for profiling. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf > Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 Applied, thanks! Best regards, Jernej > --- > changed from v3: > 1. remove wrong event mapping of 0x0000a > 2. add reference url of c906 events implementation (D1 only support events > described in R1S0 user manual, but event mapping is the same) > > changed from v2: > 1. move pmu node from /soc to / to avoid warnings when checking. > > The meaning of T-HEAD events can be found in this pending patch: > https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com > > The patch above also provides a example that shows how to setup > environment and use perf with T-HEAD events. > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 8275630af977..53a984d78e3f 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 { > #interrupt-cells = <2>; > }; > }; > + > + pmu { > + compatible = "riscv,pmu"; > + riscv,event-to-mhpmcounters = > + <0x00003 0x00003 0x00000008>, > + <0x00004 0x00004 0x00000010>, > + <0x00005 0x00005 0x00000200>, > + <0x00006 0x00006 0x00000100>, > + <0x10000 0x10000 0x00004000>, > + <0x10001 0x10001 0x00008000>, > + <0x10002 0x10002 0x00010000>, > + <0x10003 0x10003 0x00020000>, > + <0x10019 0x10019 0x00000040>, > + <0x10021 0x10021 0x00000020>; > + riscv,event-to-mhpmevent = > + <0x00003 0x00000000 0x00000001>, > + <0x00004 0x00000000 0x00000002>, > + <0x00005 0x00000000 0x00000007>, > + <0x00006 0x00000000 0x00000006>, > + <0x10000 0x00000000 0x0000000c>, > + <0x10001 0x00000000 0x0000000d>, > + <0x10002 0x00000000 0x0000000e>, > + <0x10003 0x00000000 0x0000000f>, > + <0x10019 0x00000000 0x00000004>, > + <0x10021 0x00000000 0x00000003>; > + riscv,raw-event-to-mhpmcounters = > + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, > + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, > + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, > + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, > + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, > + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, > + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, > + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, > + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, > + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, > + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > + }; > }; > -- > 2.42.0 > >
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 8275630af977..53a984d78e3f 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 { #interrupt-cells = <2>; }; }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0x00000008>, + <0x00004 0x00004 0x00000010>, + <0x00005 0x00005 0x00000200>, + <0x00006 0x00006 0x00000100>, + <0x10000 0x10000 0x00004000>, + <0x10001 0x10001 0x00008000>, + <0x10002 0x10002 0x00010000>, + <0x10003 0x10003 0x00020000>, + <0x10019 0x10019 0x00000040>, + <0x10021 0x10021 0x00000020>; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000001>, + <0x00004 0x00000000 0x00000002>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; + }; };
D1 has several pmu events supported by opensbi. These events can be used by perf for profiling. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 --- changed from v3: 1. remove wrong event mapping of 0x0000a 2. add reference url of c906 events implementation (D1 only support events described in R1S0 user manual, but event mapping is the same) changed from v2: 1. move pmu node from /soc to / to avoid warnings when checking. The meaning of T-HEAD events can be found in this pending patch: https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com The patch above also provides a example that shows how to setup environment and use perf with T-HEAD events. --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) -- 2.42.0