| Message ID | IA1PR20MB49537B6A093A491116442709BBD5A@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add Huashan Pi board support | expand |
On 2023/10/19 7:18, Inochi Amaoto wrote: > Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> LGTM. Acked-by: Chen Wang <unicorn_wang@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > new file mode 100644 > index 000000000000..3e7a942f5c1a > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > @@ -0,0 +1,24 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include "cv18xx.dtsi" > + > +/ { > + compatible = "sophgo,cv1812h"; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x10000000>; > + }; > +}; > + > +&plic { > + compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; > +}; > + > +&clint { > + compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > +}; > -- > 2.42.0 >
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi new file mode 100644 index 000000000000..3e7a942f5c1a --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include "cv18xx.dtsi" + +/ { + compatible = "sophgo,cv1812h"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&plic { + compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; +}; + +&clint { + compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; +};
Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi -- 2.42.0