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Wed, 18 Oct 2023 23:18:54 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263%5]) with mapi id 15.20.6907.021; Wed, 18 Oct 2023 23:18:54 +0000 From: Inochi Amaoto To: Chao Wei , Chen Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Jisheng Zhang , Inochi Amaoto , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc Date: Thu, 19 Oct 2023 07:18:51 +0800 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: X-TMN: [3uzAu3jYS2COcaHVvtN6QcvsWi+5/1Lfo1W8zkEPw4c=] X-ClientProxiedBy: BYAPR07CA0084.namprd07.prod.outlook.com (2603:10b6:a03:12b::25) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20231018231855.28472-4-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|DM4PR20MB5087:EE_ X-MS-Office365-Filtering-Correlation-Id: e38dc7f4-3002-43d4-4028-08dbd03098d0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fJAaQEmJ1w1d/l4zeir1rsf9+j2jLycIEbsZRn1aMq7GEbE8+LFevMor4gUuuLzhAYn0tkeyNziHSAT2ueFvi2UuEQuE+sQv0WFjgZB1pT8JhkkQWweQBzRhiMrAz5n5kA9YM9rW8oxX1LaJzAB6qySf0RRk0h06MbznKKDIDCZq5fhVSOnHyWOePDjqywIySDxJT1nOdwxpQ+LpxB4HCpbMWlUfxclWV7gF/LNKXESMNZbtvbfHUPjNIHg+Z3Y42czrUJ3is29Z/egDZweEjcyv3pRM02BI5JLN997MottggLJWI+dRzqhkkMUMLrC37M920fZQnaJwkROmQpP0K9BoFNONoarC+tmo0DKWEFm0LaEbkhBoBBYehuqroCS14dPQATu7gB0pMmGEBt88avLZo/l2kN56odqaPHJXVLGzDRCy23O2JRE5vcugHkSwY0HEiqxNwEsQzweygetSRyabsAdMl6YmewyNyEaNUl83hZ5akRjebK7zf65mpgrapxkRsPJGHuONxdAUDq3EHTWLGcygOwBByVNQ6+dlnA8jJZMLcz/TVm01vxELu9utRdphrGd6OsWyZZMzL6WHavRbb8LHZYCEjbZltPU3JQm6H5pltz8Bp6sKJNxj2owG X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZGzpKBZqtJTjeHOLEBFv3mI5El1i9crWaleCFVXK2HPCmry3mQy8UViCauY6ECWnBLvZT1TAfduVNxI5iTFxeFPWGViO8vimsbJRu9+/jjjFKqycT+pkNrV4F7/b/osS1UjeDELeRYZowlNS2V+i5OCHz/9il539UmuhXhvhT35fajl0e2ETDYDJTk+B3th0e2eJ1oWcjvrJuiqmJ63rI11cCMaEwUWpTuFo4iDpP620P1y5mIUQtcRxxVLhLnZCHJ+vtQZo7+5zD+0VwytwyOvI3n7i1az3ZYQaaINSWBDeN0hOSrwX0uwAWHPbijlX/uJLxiwSS0kZjnj7+KhUzWoubkKL4OPy4K6+vXTxR3Vk2oMVWNSH1AtmeyP5Q985lyRezvw9RLNBJfROvbUAO+Otmd9OiOQLpVjxIZir+7LOrdAG7VGsqVaJNPHJF9Bnw2C787khN6BqQyks9jPZ1JZqAVxMe2KL+q8kO9y3o9PEKPlcx+P/hlks5fhFjVmQvJx49skCefcwXTbak61FAblFZPk+1OnIOAPKbEMHakDVdni0zTMIHqPYP1K+Ell7iUQKwH3HNx8ZWoZkL2w3w0XutGZhGBJqBmG1iwqsZ1ceB8jRvluy863JACxaWbunTx2V8uGjaVa8Qtv4L+DtzQzawaGfqzX+i22ym1/Hv+OHNi7YbTZmX5wP3KY1JVQlOW4TUXKOymkatVYo7YSUJtAHpX5JYiVCXmQePlWSc9prDVHLy2wdi7nazU7mDh99Ai5iuEYjqpqGVKryvVFEsgqjnbBFgHlm13+O2HXrxvqHMaOicAobEZsXsPcnOOOwDpJl5EwqTii3jPBIjdKUhxK7r593hlb76gMnqc8Kp8fimWOgjOFvgGnpDYoTaFVbsD/mIL0aI9uc3Dd8Q/HyozebSwxkJI6qZNT2KTQoSKmDbyqAsfKSSwsHlUQ67Vnrp7WEuLrVCwKzj5JRFGvDccAJ7Z5OrE/derLhybYdC7HnnKWviEQNhWp3mopMIFO0ghheWNtpY7N2KBE6tTOuLk8JTQ2rC26YNxOBgErOyI3aCHZ/L4T0z7bqY5VBSec7NCYOqVArO1NNSli9unOqgAaJQxYXZ8StliUZ5jCeU9ad6AYD2w7VmLDV3/UQLvLNF8vmY7/8KJLfrtHYBPL0GvxSuTcn/LukwmoTB0spdNBSrPUd67ewvmIq82DeavN2a2HKMvfCP3wG0ftFuPIkSEqkZCgN5bAlIyZ/lnIagdk= X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e38dc7f4-3002-43d4-4028-08dbd03098d0 X-MS-Exchange-CrossTenant-AuthSource: IA1PR20MB4953.namprd20.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2023 23:18:54.5918 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR20MB5087 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_161858_260944_604650E2 X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As CV180x and CV181x have the identical layouts, it is OK to use the cv1800b basic device tree for the whole series. For CV1800B soc specific compatible, just move them out of the common file. Signed-off-by: Inochi Amaoto Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 ++--------------------- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 120 ++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 112 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi -- 2.42.0 diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..165e9e320a8c 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,121 +3,16 @@ * Copyright (C) 2023 Jisheng Zhang */ -#include +#include "cv18xx.dtsi" / { compatible = "sophgo,cv1800b"; - #address-cells = <1>; - #size-cells = <1>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <25000000>; - - cpu0: cpu@0 { - compatible = "thead,c906", "riscv"; - device_type = "cpu"; - reg = <0>; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <65536>; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - mmu-type = "riscv,sv39"; - riscv,isa = "rv64imafdc"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_25m"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <1>; - #size-cells = <1>; - dma-noncoherent; - ranges; - - uart0: serial@4140000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04140000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@4150000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04150000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@4160000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04160000 0x100>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@4170000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04170000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@41c0000 { - compatible = "snps,dw-apb-uart"; - reg = <0x041c0000 0x100>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; +}; - plic: interrupt-controller@70000000 { - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; - reg = <0x70000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <101>; - }; +&plic { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; +}; - clint: timer@74000000 { - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; - reg = <0x74000000 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; - }; - }; +&clint { + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; }; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi new file mode 100644 index 000000000000..55d4bc84faa0 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@4150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@4160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@4170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@41c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +};