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[GIT,PULL] RISC-V Sophgo Devicetrees for v6.11

Message ID PN1P287MB281861EA2B1706B430D2FA3EFEDB2@PN1P287MB2818.INDP287.PROD.OUTLOOK.COM (mailing list archive)
State Handled Elsewhere
Headers show
Series [GIT,PULL] RISC-V Sophgo Devicetrees for v6.11 | expand

Pull-request

https://github.com/sophgo/linux.git tags/riscv-sophgo-dt-for-v6.11

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Message

Chen Wang July 9, 2024, 12:39 a.m. UTC 
Hey Arnd,

Please pull dt changes for RISC-V/Sophgo.

I hope this PR is not too late, because I just got the message today 
from Stephen that this clock driver part has been merged into clk-next.

Just FYI: 
https://lore.kernel.org/linux-riscv/b8dbdde2412d974baa24611b16cda5f7.sboyd@kernel.org/


Thanks,
Chen.

The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0:

   Linux 6.10-rc1 (2024-05-26 15:20:12 -0700)

are available in the Git repository at:

   https://github.com/sophgo/linux.git tags/riscv-sophgo-dt-for-v6.11

for you to fetch changes up to b1240a39511b9206293b82ac372c5114d6e15821:

   riscv: dts: add clock generator for Sophgo SG2042 SoC (2024-07-09 
08:19:52 +0800)

----------------------------------------------------------------
RISC-V Devicetrees for v6.11

Sopgho:
Add clock support for SG2042.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

----------------------------------------------------------------
Chen Wang (1):
       riscv: dts: add clock generator for Sophgo SG2042 SoC

  arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++
  arch/riscv/boot/dts/sophgo/sg2042.dtsi              | 55 
++++++++++++++++++++++++++++++++++++++++++++++++++++++-
  2 files changed, 66 insertions(+), 1 deletion(-)