| Message ID | SYBP282MB22389FD1E07BBDC6FE1D90A0C4CE2@SYBP282MB2238.AUSP282.PROD.OUTLOOK.COM (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: sophgo: add mailbox support for cv18x SoCs | expand |
On Tue, Jun 18, 2024 at 11:12:33PM +0800, Yuntao Dai wrote: > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > --- > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > new file mode 100644 > index 000000000..e1868aaf2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo cv1800b mailbox controller > + > +maintainers: > + - Yuntao Dai <d1581209858@live.com> > + > +description: > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > + different processors. Any processer can write data in a channel, and > + set co-responding register to raise interrupt to notice another processor, > + and it is allowed to send data to itself. > + Sophgo cv18x SoCs has 3 processors and numbered as > + <1> C906L > + <2> C906B > + <3> 8051 > + > +properties: > + compatible: > + enum: > + - sophgo,cv1800b-mailbox > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + const: mailbox > + > + recvid: > + maxItems: 1 > + description: > + This cell indicates the mailbox controller is running on which processor You can just look up your hartid at runtime, wouldn't that be sufficient? > + > + sendto: > + maxItems: 1 > + description: > + This cell indicates the message sends to which processor Can't this go into an mbox cell? Having this property would limit the mailbox to only communicating with 1 of the 2 available processors. Cheers, Conor. > + > + > + "#mbox-cells": > + const: 1 > + description: > + This cell indicates which channel is used > + > +required: > + - compatible > + - reg > + - interrupts > + - recvid > + - sendto > + - "#mbox-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + > + mailbox: mailbox@1900000 { > + compatible = "sophgo,cv1800b-mailbox"; > + reg = <0x01900000 0x1000>; > + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mailbox"; > + interrupt-parent = <&plic>; > + recvid = <1>; > + sendto = <2>; > + #mbox-cells = <1>; > + }; > -- > 2.17.1 >
On Tue, 18 Jun 2024 23:12:33 +0800, Yuntao Dai wrote: > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > --- > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml: recvid: missing type definition /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml: sendto: missing type definition doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/SYBP282MB22389FD1E07BBDC6FE1D90A0C4CE2@SYBP282MB2238.AUSP282.PROD.OUTLOOK.COM The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Tue, Jun 18, 2024 at 11:12:33PM GMT, Yuntao Dai wrote: > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > --- > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > new file mode 100644 > index 000000000..e1868aaf2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo cv1800b mailbox controller > + > +maintainers: > + - Yuntao Dai <d1581209858@live.com> > + > +description: > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > + different processors. Any processer can write data in a channel, and > + set co-responding register to raise interrupt to notice another processor, > + and it is allowed to send data to itself. > + Sophgo cv18x SoCs has 3 processors and numbered as > + <1> C906L > + <2> C906B > + <3> 8051 > + > +properties: > + compatible: > + enum: > + - sophgo,cv1800b-mailbox "sophgo,cv1800-mailbox" please. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + const: mailbox > + > + recvid: > + maxItems: 1 > + description: > + This cell indicates the mailbox controller is running on which processor > + > + sendto: > + maxItems: 1 > + description: > + This cell indicates the message sends to which processor > + > + > + "#mbox-cells": > + const: 1 > + description: > + This cell indicates which channel is used > + > +required: > + - compatible > + - reg > + - interrupts > + - recvid > + - sendto > + - "#mbox-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + > + mailbox: mailbox@1900000 { > + compatible = "sophgo,cv1800b-mailbox"; > + reg = <0x01900000 0x1000>; > + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mailbox"; > + interrupt-parent = <&plic>; > + recvid = <1>; > + sendto = <2>; > + #mbox-cells = <1>; > + }; > -- > 2.17.1 >
On Tue, Jun 18, 2024 at 11:12:33PM GMT, Yuntao Dai wrote: > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > --- > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > new file mode 100644 > index 000000000..e1868aaf2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo cv1800b mailbox controller > + > +maintainers: > + - Yuntao Dai <d1581209858@live.com> > + > +description: > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > + different processors. Any processer can write data in a channel, and > + set co-responding register to raise interrupt to notice another processor, > + and it is allowed to send data to itself. > + Sophgo cv18x SoCs has 3 processors and numbered as > + <1> C906L > + <2> C906B > + <3> 8051 Are you sure the 8051 use the same mailbox layout? IIRC, only the small core use this mailbox. > + > +properties: > + compatible: > + enum: > + - sophgo,cv1800b-mailbox > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + const: mailbox > + > + recvid: > + maxItems: 1 > + description: > + This cell indicates the mailbox controller is running on which processor > + > + sendto: > + maxItems: 1 > + description: > + This cell indicates the message sends to which processor > + > + > + "#mbox-cells": > + const: 1 > + description: > + This cell indicates which channel is used > + > +required: > + - compatible > + - reg > + - interrupts > + - recvid > + - sendto > + - "#mbox-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + > + mailbox: mailbox@1900000 { > + compatible = "sophgo,cv1800b-mailbox"; > + reg = <0x01900000 0x1000>; > + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mailbox"; > + interrupt-parent = <&plic>; > + recvid = <1>; > + sendto = <2>; > + #mbox-cells = <1>; > + }; > -- > 2.17.1 >
Hi Yuntao, kernel test robot noticed the following build warnings: [auto build test WARNING on robh/for-next] [also build test WARNING on linus/master v6.10-rc4 next-20240618] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Yuntao-Dai/dt-bindings-mailbox-add-Sophgo-cv18x-SoCs-mailbox/20240618-232307 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/SYBP282MB22389FD1E07BBDC6FE1D90A0C4CE2%40SYBP282MB2238.AUSP282.PROD.OUTLOOK.COM patch subject: [PATCH 1/3] dt-bindings: mailbox: add Sophgo cv18x SoCs mailbox config: arc-randconfig-051-20240619 (https://download.01.org/0day-ci/archive/20240619/202406190627.BcUP9uUN-lkp@intel.com/config) compiler: arceb-elf-gcc (GCC) 13.2.0 dtschema version: 2024.6.dev1+g833054f reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240619/202406190627.BcUP9uUN-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406190627.BcUP9uUN-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml: recvid: missing type definition >> Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml: sendto: missing type definition
Hi Conor, > From: Conor Dooley > Sent: Tuesday, June 18, 2024 23:38 > To: Yuntao Dai > Cc: jassisinghbrar@gmail.com; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; unicorn_wang@outlook.com; inochiama@outlook.com; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org > Subject: Re: [PATCH 1/3] dt-bindings: mailbox: add Sophgo cv18x SoCs mailbox > > > On Tue, Jun 18, 2024 at 11:12:33PM +0800, Yuntao Dai wrote: > > > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > > > > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > > > --- > > > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > > > 1 file changed, 75 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > new file mode 100644 > > > index 000000000..e1868aaf2 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > @@ -0,0 +1,75 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Sophgo cv1800b mailbox controller > > > + > > > +maintainers: > > > + - Yuntao Dai <d1581209858@live.com> > > > + > > > +description: > > > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > > > + different processors. Any processer can write data in a channel, and > > > + set co-responding register to raise interrupt to notice another processor, > > > + and it is allowed to send data to itself. > > > + Sophgo cv18x SoCs has 3 processors and numbered as > > > + <1> C906L > > > + <2> C906B > > > + <3> 8051 > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - sophgo,cv1800b-mailbox > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + interrupt-names: > > > + const: mailbox > > > + > > > + recvid: > > > + maxItems: 1 > > > + description: > > > + This cell indicates the mailbox controller is running on which processor > > > > You can just look up your hartid at runtime, wouldn't that be > > sufficient? > thanks your addvice, I will fix it > > > + > > > + sendto: > > > + maxItems: 1 > > > + description: > > > + This cell indicates the message sends to which processor > > > > Can't this go into an mbox cell? Having this property would limit the > > mailbox to only communicating with 1 of the 2 available processors. > I will fix it > Cheers, > > Conor. > > > > > + > > > + > > > + "#mbox-cells": > > > + const: 1 > > > + description: > > > + This cell indicates which channel is used > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - recvid > > > + - sendto > > > + - "#mbox-cells" > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + #include <dt-bindings/interrupt-controller/irq.h> > > > + > > > + mailbox: mailbox@1900000 { > > > + compatible = "sophgo,cv1800b-mailbox"; > > > + reg = <0x01900000 0x1000>; > > > + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "mailbox"; > > > + interrupt-parent = <&plic>; > > > + recvid = <1>; > > > + sendto = <2>; > > > + #mbox-cells = <1>; > > > + }; > > > -- > > > 2.17.1 Best regards, Yuntao
Hi Rob, > On Tue, 18 Jun 2024 23:12:33 +0800, Yuntao Dai wrote: > > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > > --- > > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > > 1 file changed, 75 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml: recvid: missing type definition > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml: sendto: missing type definition > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/SYBP282MB22389FD1E07BBDC6FE1D90A0C4CE2@SYBP282MB2238.AUSP282.PROD.OUTLOOK.COM thanks your advice, I will try upgrade these tools and fix it Best regards, Yuntao
Hi Inochi, > From: Inochi Amaoto <inochiama@outlook.com> > Sent: Wednesday, 19 June 2024 06:33 > To: Yuntao Dai <d1581209858@live.com>; jassisinghbrar@gmail.com <jassisinghbrar@gmail.com>; robh@kernel.org <robh@kernel.org>; krzk+dt@kernel.org <krzk+dt@kernel.org>; conor+dt@kernel.org <conor+dt@kernel.org>; unicorn_wang@outlook.com <unicorn_wang@outlook.com>; inochiama@outlook.com <inochiama@outlook.com>; paul.walmsley@sifive.com <paul.walmsley@sifive.com>; palmer@dabbelt.com <palmer@dabbelt.com>; aou@eecs.berkeley.edu <aou@eecs.berkeley.edu> > Cc: linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; devicetree@vger.kernel.org <devicetree@vger.kernel.org>; linux-riscv@lists.infradead.org <linux-riscv@lists.infradead.org> > Subject: Re: [PATCH 1/3] dt-bindings: mailbox: add Sophgo cv18x SoCs mailbox > > On Tue, Jun 18, 2024 at 11:12:33PM GMT, Yuntao Dai wrote: > > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > > --- > > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > > 1 file changed, 75 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > new file mode 100644 > > index 000000000..e1868aaf2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > @@ -0,0 +1,75 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Sophgo cv1800b mailbox controller > > + > > +maintainers: > > + - Yuntao Dai <d1581209858@live.com> > > + > > +description: > > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > > + different processors. Any processer can write data in a channel, and > > + set co-responding register to raise interrupt to notice another processor, > > + and it is allowed to send data to itself. > > + Sophgo cv18x SoCs has 3 processors and numbered as > > + <1> C906L > > + <2> C906B > > + <3> 8051 > > + > > +properties: > > + compatible: > > + enum: > > + - sophgo,cv1800b-mailbox > > "sophgo,cv1800-mailbox" please. > I will fix it > > + > > + reg: > > + maxItems: 1 > > -- > > 2.17.1 > > Best regards, Yuntao Dai
On Wed, Jun 19, 2024 at 02:33:46PM +0000, 韵涛 代 wrote: > Hi Conor, Something has gone fairly badly wrong with your mail client FYI: > > > From: Conor Dooley > > Sent: Tuesday, June 18, 2024 23:38 > > To: Yuntao Dai > > Cc: jassisinghbrar@gmail.com; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; unicorn_wang@outlook.com; inochiama@outlook.com; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org > > Subject: Re: [PATCH 1/3] dt-bindings: mailbox: add Sophgo cv18x SoCs mailbox > > > > > > On Tue, Jun 18, 2024 at 11:12:33PM +0800, Yuntao Dai wrote: > > > > > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > > > > > > > > > Signed-off-by: Yuntao Dai <d1581209858@live.com> > > > > > --- > > > > > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > > > > > 1 file changed, 75 insertions(+) > > > > > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > > new file mode 100644 > > > > > index 000000000..e1868aaf2 > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > > @@ -0,0 +1,75 @@ > > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > > +%YAML 1.2 > > > > > +--- > > > > > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > + > > > > > +title: Sophgo cv1800b mailbox controller > > > > > + > > > > > +maintainers: > > > > > + - Yuntao Dai <d1581209858@live.com> > > > > > + > > > > > +description: > > > > > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > > > > > + different processors. Any processer can write data in a channel, and > > > > > + set co-responding register to raise interrupt to notice another processor, > > > > > + and it is allowed to send data to itself. > > > > > + Sophgo cv18x SoCs has 3 processors and numbered as > > > > > + <1> C906L > > > > > + <2> C906B > > > > > + <3> 8051 > > > > > + > > > > > +properties: > > > > > + compatible: > > > > > + enum: > > > > > + - sophgo,cv1800b-mailbox > > > > > + > > > > > + reg: > > > > > + maxItems: 1 > > > > > + > > > > > + interrupts: > > > > > + maxItems: 1 > > > > > + > > > > > + interrupt-names: > > > > > + const: mailbox > > > > > + > > > > > + recvid: > > > > > + maxItems: 1 > > > > > + description: > > > > > + This cell indicates the mailbox controller is running on which processor > > > > > > > > You can just look up your hartid at runtime, wouldn't that be > > > > sufficient? > > > > thanks your addvice, I will fix it This advice may or may not be correct, that's why I put a ? at the end. If the hart id of both the C906L and C906B are identical, looking the hart up at runtime isn't going to help you. If they're different, cpuid_to_hartid_map(0) will give you the info I believe.
Hi Inochi, Sorry for replying late, I have been waiting for the vendor to make their mailbox document public, but they haven't done it yet. On Wed, Jun 19, 2024 at 6:45 AM, Inochi Amaoto <inochiama@outlook.com> wrote: > On Tue, Jun 18, 2024 at 11:12:33PM GMT, Yuntao Dai wrote: >> Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox >> >> Signed-off-by: Yuntao Dai <d1581209858@live.com> >> --- >> .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 >> +++++++++++++++++++ >> 1 file changed, 75 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml >> >> diff --git >> a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml >> b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml >> new file mode 100644 >> index 000000000..e1868aaf2 >> --- /dev/null >> +++ >> b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml >> @@ -0,0 +1,75 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: >> http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Sophgo cv1800b mailbox controller >> + >> +maintainers: >> + - Yuntao Dai <d1581209858@live.com> >> + >> +description: >> + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per >> channel for >> + different processors. Any processer can write data in a channel, >> and >> + set co-responding register to raise interrupt to notice another >> processor, >> + and it is allowed to send data to itself. >> + Sophgo cv18x SoCs has 3 processors and numbered as >> + <1> C906L >> + <2> C906B >> + <3> 8051 > > Are you sure the 8051 use the same mailbox layout? > IIRC, only the small core use this mailbox. Yes, I am sure of this, and cv18xx SoCs and sg200x SoCs share the same mailbox IP >> + >> +properties: >> + compatible: >> + enum: >> + - sophgo,cv1800b-mailbox >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-names: >> + const: mailbox >> + >> + recvid: >> + maxItems: 1 >> + description: >> + This cell indicates the mailbox controller is running on >> which processor >> + >> + sendto: >> + maxItems: 1 >> + description: >> + This cell indicates the message sends to which processor >> + >> + >> + "#mbox-cells": >> + const: 1 >> + description: >> + This cell indicates which channel is used >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - recvid >> + - sendto >> + - "#mbox-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/irq.h> >> + >> + mailbox: mailbox@1900000 { >> + compatible = "sophgo,cv1800b-mailbox"; >> + reg = <0x01900000 0x1000>; >> + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "mailbox"; >> + interrupt-parent = <&plic>; >> + recvid = <1>; >> + sendto = <2>; >> + #mbox-cells = <1>; >> + }; >> -- >> 2.17.1 >>
diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml new file mode 100644 index 000000000..e1868aaf2 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo cv1800b mailbox controller + +maintainers: + - Yuntao Dai <d1581209858@live.com> + +description: + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for + different processors. Any processer can write data in a channel, and + set co-responding register to raise interrupt to notice another processor, + and it is allowed to send data to itself. + Sophgo cv18x SoCs has 3 processors and numbered as + <1> C906L + <2> C906B + <3> 8051 + +properties: + compatible: + enum: + - sophgo,cv1800b-mailbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: mailbox + + recvid: + maxItems: 1 + description: + This cell indicates the mailbox controller is running on which processor + + sendto: + maxItems: 1 + description: + This cell indicates the message sends to which processor + + + "#mbox-cells": + const: 1 + description: + This cell indicates which channel is used + +required: + - compatible + - reg + - interrupts + - recvid + - sendto + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + mailbox: mailbox@1900000 { + compatible = "sophgo,cv1800b-mailbox"; + reg = <0x01900000 0x1000>; + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mailbox"; + interrupt-parent = <&plic>; + recvid = <1>; + sendto = <2>; + #mbox-cells = <1>; + };
Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox Signed-off-by: Yuntao Dai <d1581209858@live.com> --- .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml