| Message ID | alpine.DEB.2.21.9999.1906260829030.21507@viisi.sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: riscv: resolve 'make dt_binding_check' warnings | expand |
On Wed, Jun 26, 2019 at 9:30 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > > Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema > results in warnings from 'make dt_binding_check'. Fix these. > > While here, make the whitespace in the second example consistent with the > first example. > > Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> > Cc: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- > 1 file changed, 14 insertions(+), 12 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 27f02ec4bb45..f97a4ecd7b91 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -152,17 +152,19 @@ examples: > - | > // Example 2: Spike ISA Simulator with 1 Hart > cpus { > - cpu@0 { > - device_type = "cpu"; > - reg = <0>; > - compatible = "riscv"; > - riscv,isa = "rv64imafdc"; > - mmu-type = "riscv,sv48"; > - interrupt-controller { > - #interrupt-cells = <1>; > - interrupt-controller; > - compatible = "riscv,cpu-intc"; > - }; > - }; > + #address-cells = <1>; > + #size-cells = <0>; > + cpu@0 { This only works because you removed 'cpus' and therefore none of this schema is applied. > + device_type = "cpu"; > + reg = <0>; > + compatible = "riscv"; According to the schema, this is wrong. It should have 2 strings. Or the schema needs to allow this case, but 'riscv' is too vague to be very useful. Also, I noticed that there's still a riscv/cpus.txt. That should be removed and replaced with this file. Looks like the hart description at least should be copied over (into top-level 'description'). > + riscv,isa = "rv64imafdc"; > + mmu-type = "riscv,sv48"; > + interrupt-controller { > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "riscv,cpu-intc"; > + }; > + }; > }; > ... > -- > 2.20.1 >
On Wed, 26 Jun 2019, Rob Herring wrote: > On Wed, Jun 26, 2019 at 9:30 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > > > Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema > > results in warnings from 'make dt_binding_check'. Fix these. > > > > While here, make the whitespace in the second example consistent with the > > first example. > > > > Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> > > Cc: Rob Herring <robh@kernel.org> > > --- > > .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- > > 1 file changed, 14 insertions(+), 12 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index 27f02ec4bb45..f97a4ecd7b91 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -152,17 +152,19 @@ examples: > > - | > > // Example 2: Spike ISA Simulator with 1 Hart > > cpus { > > - cpu@0 { > > - device_type = "cpu"; > > - reg = <0>; > > - compatible = "riscv"; > > - riscv,isa = "rv64imafdc"; > > - mmu-type = "riscv,sv48"; > > - interrupt-controller { > > - #interrupt-cells = <1>; > > - interrupt-controller; > > - compatible = "riscv,cpu-intc"; > > - }; > > - }; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + cpu@0 { > > This only works because you removed 'cpus' and therefore none of this > schema is applied. I'm not following you - could you point out where "cpus" was removed? > > + device_type = "cpu"; > > + reg = <0>; > > + compatible = "riscv"; > > According to the schema, this is wrong. It should have 2 strings. Or > the schema needs to allow this case, but 'riscv' is too vague to be > very useful. OK, I'll come up with something for Spike. > Also, I noticed that there's still a riscv/cpus.txt. That should be > removed and replaced with this file. Looks like the hart description > at least should be copied over (into top-level 'description'). OK, will do that when I hear back from you. - Paul
On Wed, 26 Jun 2019, Paul Walmsley wrote: > On Wed, 26 Jun 2019, Rob Herring wrote: > > > On Wed, Jun 26, 2019 at 9:30 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > > > > > Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema > > > results in warnings from 'make dt_binding_check'. Fix these. > > > > > > While here, make the whitespace in the second example consistent with the > > > first example. > > > > > > Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> > > > Cc: Rob Herring <robh@kernel.org> > > > --- > > > .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- > > > 1 file changed, 14 insertions(+), 12 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index 27f02ec4bb45..f97a4ecd7b91 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -152,17 +152,19 @@ examples: > > > - | > > > // Example 2: Spike ISA Simulator with 1 Hart > > > cpus { > > > - cpu@0 { > > > - device_type = "cpu"; > > > - reg = <0>; > > > - compatible = "riscv"; > > > - riscv,isa = "rv64imafdc"; > > > - mmu-type = "riscv,sv48"; > > > - interrupt-controller { > > > - #interrupt-cells = <1>; > > > - interrupt-controller; > > > - compatible = "riscv,cpu-intc"; > > > - }; > > > - }; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + cpu@0 { > > > > This only works because you removed 'cpus' and therefore none of this > > schema is applied. > > I'm not following you - could you point out where "cpus" was removed? If it helps, this patch is simply to fix the dtc warnings that you mentioned in your post on devicetree-spec@. Without this patch, with "make dtbs_check", the following warnings are generated: DTC Documentation/devicetree/bindings/riscv/cpus.example.dtb Documentation/devicetree/bindings/riscv/cpus.example.dts:75.25-35: Warning (reg_format): /example-1/cpus/cpu@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Documentation/devicetree/bindings/riscv/cpus.example.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' Documentation/devicetree/bindings/riscv/cpus.example.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' Documentation/devicetree/bindings/riscv/cpus.example.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' Documentation/devicetree/bindings/riscv/cpus.example.dts:73.23-84.19: Warning (avoid_default_addr_size): /example-1/cpus/cpu@0: Relying on default #address-cells value Documentation/devicetree/bindings/riscv/cpus.example.dts:73.23-84.19: Warning (avoid_default_addr_size): /example-1/cpus/cpu@0: Relying on default #size-cells value When the patch is applied, dtc doesn't report any of these warnings. Let me know if I'm missing something obvious. - Paul
On Wed, Jun 26, 2019 at 2:27 PM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > On Wed, 26 Jun 2019, Rob Herring wrote: > > > On Wed, Jun 26, 2019 at 9:30 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > > > > > Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema > > > results in warnings from 'make dt_binding_check'. Fix these. > > > > > > While here, make the whitespace in the second example consistent with the > > > first example. > > > > > > Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> > > > Cc: Rob Herring <robh@kernel.org> > > > --- > > > .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- > > > 1 file changed, 14 insertions(+), 12 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index 27f02ec4bb45..f97a4ecd7b91 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -152,17 +152,19 @@ examples: > > > - | > > > // Example 2: Spike ISA Simulator with 1 Hart > > > cpus { > > > - cpu@0 { > > > - device_type = "cpu"; > > > - reg = <0>; > > > - compatible = "riscv"; > > > - riscv,isa = "rv64imafdc"; > > > - mmu-type = "riscv,sv48"; > > > - interrupt-controller { > > > - #interrupt-cells = <1>; > > > - interrupt-controller; > > > - compatible = "riscv,cpu-intc"; > > > - }; > > > - }; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + cpu@0 { > > > > This only works because you removed 'cpus' and therefore none of this > > schema is applied. > > I'm not following you - could you point out where "cpus" was removed? Sorry, I guess the indentation change threw me off... For fixing the dtc warnings: Reviewed-by: Rob Herring <robh@kernel.org>
On Wed, 26 Jun 2019, Rob Herring wrote: > Sorry, I guess the indentation change threw me off... > > For fixing the dtc warnings: > > Reviewed-by: Rob Herring <robh@kernel.org> Thanks, I've queued the following patch for v5.2-rc. Will address the schema-related issues in separate patches. - Paul From: Paul Walmsley <paul.walmsley@sifive.com> Date: Wed, 26 Jun 2019 08:19:29 -0700 Subject: [PATCH] dt-bindings: riscv: resolve 'make dt_binding_check' warnings Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema results in warnings from 'make dt_binding_check'. Fix these. While here, make the whitespace in the second example consistent with the first example. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Rob Herring <robh@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> # for fixing the dtc warnings --- .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 27f02ec4bb45..f97a4ecd7b91 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -152,17 +152,19 @@ examples: - | // Example 2: Spike ISA Simulator with 1 Hart cpus { - cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv48"; - interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; ...
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 27f02ec4bb45..f97a4ecd7b91 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -152,17 +152,19 @@ examples: - | // Example 2: Spike ISA Simulator with 1 Hart cpus { - cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv48"; - interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; ...
Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema results in warnings from 'make dt_binding_check'. Fix these. While here, make the whitespace in the second example consistent with the first example. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-)