diff mbox series

[1/3] dt-bindings: reset: sifive: add fu540/fu740 reset indexes

Message ID d4e3c23469fbddb6904b857e9d262d86aecbd880.1724827635.git.ganboing@gmail.com (mailing list archive)
State Handled Elsewhere
Delegated to: Conor Dooley
Headers show
Series clk: sifive: Fix chip hang when booting linux directly | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-1-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-1-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-1-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-1-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-1-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-1-test-6 warning .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-1-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-1-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-1-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-1-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-1-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-1-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Bo Gan Aug. 28, 2024, 6:55 a.m. UTC
Add bindings for FU540/FU740 clock/reset controller. The header is taken
from the same path in U-Boot with macros renamed to have FU540/740 prefix.

Signed-off-by: Bo Gan <ganboing@gmail.com>
---
 include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++
 include/dt-bindings/reset/sifive-fu740-prci.h | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h
 create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h

Comments

Krzysztof Kozlowski Aug. 29, 2024, 5:56 a.m. UTC | #1
On 28/08/2024 08:55, Bo Gan wrote:
> Add bindings for FU540/FU740 clock/reset controller. The header is taken
> from the same path in U-Boot with macros renamed to have FU540/740 prefix.
> 
> Signed-off-by: Bo Gan <ganboing@gmail.com>
> ---
>  include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++
>  include/dt-bindings/reset/sifive-fu740-prci.h | 19 +++++++++++++++++++
>  2 files changed, 38 insertions(+)
>  create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h
>  create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h
> 
> diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h
> new file mode 100644
> index 000000000000..dbaf602262d2
> --- /dev/null
> +++ b/include/dt-bindings/reset/sifive-fu540-prci.h

Filename matching compatible.

> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license.


Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h
new file mode 100644
index 000000000000..dbaf602262d2
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu540-prci.h
@@ -0,0 +1,19 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Sifive, Inc.
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define FU540_PRCI_RST_DDR_CTRL_N	0
+#define FU540_PRCI_RST_DDR_AXI_N	1
+#define FU540_PRCI_RST_DDR_AHB_N	2
+#define FU540_PRCI_RST_DDR_PHY_N	3
+/* bit 4 is reserved bit */
+#define FU540_PRCI_RST_RSVD_N		4
+#define FU540_PRCI_RST_GEMGXL_N		5
+
+#endif
diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h
new file mode 100644
index 000000000000..74d60ca9f1df
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu740-prci.h
@@ -0,0 +1,19 @@ 
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2020-2021 Sifive, Inc.
+ * Author: Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define FU740_PRCI_RST_DDR_CTRL_N	0
+#define FU740_PRCI_RST_DDR_AXI_N	1
+#define FU740_PRCI_RST_DDR_AHB_N	2
+#define FU740_PRCI_RST_DDR_PHY_N	3
+#define FU740_PRCI_RST_PCIE_POWER_UP_N	4
+#define FU740_PRCI_RST_GEMGXL_N		5
+#define FU740_PRCI_RST_CLTX_N		6
+
+#endif