| Message ID | fec7163144d7f7b615695b5fd22a182ed7f1e7e9.1729037302.git.unicorn_wang@outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | pwm: Add pwm driver for Sophgo SG2042 | expand |
On Wed, Oct 16, 2024 at 08:19:22AM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Sophgo SG2042 contains a PWM controller, which has 4 channels and > can generate PWM waveforms output. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/pwm/sophgo,sg2042-pwm.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml > new file mode 100644 > index 000000000000..fe89719ed9dd > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 PWM controller > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +description: > + This controller contains 4 channels which can generate PWM waveforms. > + > +allOf: > + - $ref: pwm.yaml# > + > +properties: > + compatible: > + const: sophgo,sg2042-pwm > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: apb > + > + "#pwm-cells": > + const: 2 > + Does this ip need a reset? I see a RST_PWM in the reset bindings. If so, please add reset support for the whole patch. > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + pwm@7f006000 { > + compatible = "sophgo,sg2042-pwm"; > + reg = <0x7f006000 0x1000>; > + #pwm-cells = <2>; > + clocks = <&clock 67>; > + clock-names = "apb"; > + }; > -- > 2.34.1 >
On 2024/10/25 11:28, Inochi Amaoto wrote: > On Wed, Oct 16, 2024 at 08:19:22AM +0800, Chen Wang wrote: [......] > Does this ip need a reset? I see a RST_PWM in the reset bindings. > If so, please add reset support for the whole patch. Yes, we need it, I will provide a fix patch quickly. Thanks, Chen >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + pwm@7f006000 { >> + compatible = "sophgo,sg2042-pwm"; >> + reg = <0x7f006000 0x1000>; >> + #pwm-cells = <2>; >> + clocks = <&clock 67>; >> + clock-names = "apb"; >> + }; >> -- >> 2.34.1 >>
diff --git a/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml new file mode 100644 index 000000000000..fe89719ed9dd --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PWM controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +description: + This controller contains 4 channels which can generate PWM waveforms. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,sg2042-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + pwm@7f006000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x7f006000 0x1000>; + #pwm-cells = <2>; + clocks = <&clock 67>; + clock-names = "apb"; + };