mbox series

[GIT,PULL] RISC-V Fixes for 6.7-rc5

Message ID mhng-1c062b80-96c4-4146-a689-9338ce7c524c@palmer-ri-x1c9 (mailing list archive)
State Handled Elsewhere
Headers show
Series [GIT,PULL] RISC-V Fixes for 6.7-rc5 | expand

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.7-rc5

Message

Palmer Dabbelt Dec. 8, 2023, 4:09 p.m. UTC 
The following changes since commit b85ea95d086471afb4ad062012a4d73cd328fa86:

  Linux 6.7-rc1 (2023-11-12 16:19:07 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.7-rc5

for you to fetch changes up to ed5b7cfd7839f9280a63365c1133482b42d0981f:

  riscv: errata: andes: Probe for IOCP only once in boot stage (2023-12-06 07:18:58 -0800)

----------------------------------------------------------------
RISC-V Fixes for 6.7-rc5

* A pair of fixes to the new module load-time relocation code.
* A fix for hwprobe overflowing on rv32.
* A fix for to correctly decode C.SWSP and C.SDSP, which manifests in
  misaligned access handling.
* A fix for a boot-time shadow call stack initialization ordering issue.
* A fix for Andes' errata probing, which was calling
  riscv_noncoherent_supported() too late in the boot process and
  triggering an oops.

----------------------------------------------------------------
This is all a bit big for rc5, but I think it's really just up to me being out
for a bit around Plumbers and Thanksgiving.

----------------------------------------------------------------
Andrew Jones (1):
      RISC-V: hwprobe: Always use u64 for extension bits

Charlie Jenkins (3):
      riscv: Safely remove entries from relocation list
      riscv: Correct type casting in module loading
      Support rv32 ULEB128 test

Clément Léger (1):
      riscv: fix misaligned access handling of C.SWSP and C.SDSP

Lad Prabhakar (1):
      riscv: errata: andes: Probe for IOCP only once in boot stage

Palmer Dabbelt (1):
      Merge patch series "riscv: Fix issues with module loading"

Rob Herring (1):
      dt-bindings: perf: riscv,pmu: drop unneeded quotes

Samuel Holland (1):
      riscv: Fix SMP when shadow call stacks are enabled

 .../devicetree/bindings/perf/riscv,pmu.yaml        |   2 +-
 arch/riscv/errata/andes/errata.c                   |  20 ++--
 arch/riscv/kernel/head.S                           |   2 +-
 arch/riscv/kernel/module.c                         | 114 +++++++++++++++------
 arch/riscv/kernel/sys_riscv.c                      |   2 +-
 arch/riscv/kernel/tests/module_test/test_uleb128.S |   8 +-
 arch/riscv/kernel/traps_misaligned.c               |   6 +-
 7 files changed, 106 insertions(+), 48 deletions(-)

Comments

pr-tracker-bot@kernel.org Dec. 8, 2023, 5:08 p.m. UTC | #1 
The pull request you sent on Fri, 08 Dec 2023 08:09:19 -0800 (PST):

> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.7-rc5

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4df7c5fde316820286dfa6d203a1005d7fbe007d

Thank you!