| Message ID | mhng-9a7c8503-91d4-4b92-a594-964a5983ecab@palmer-ri-x1c9 (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [GIT,PULL] RISC-V Patches for the 6.8 Merge Window, Part 1 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
The pull request you sent on Fri, 12 Jan 2024 09:02:42 -0800 (PST):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.8-mw1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4331f070267ae8f76db1abbc7f4eeed4f06ae817
Thank you!
The following changes since commit ed5b7cfd7839f9280a63365c1133482b42d0981f: riscv: errata: andes: Probe for IOCP only once in boot stage (2023-12-06 07:18:58 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.8-mw1 for you to fetch changes up to cb51bfee7f62a8e26b694f9d84c0041b3e3ccc71: Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support" (2024-01-09 20:14:51 -0800) ---------------------------------------------------------------- RISC-V Patches for the 6.8 Merge Window, Part 1 * Support for many new extensions in hwprobe, along with a handful of cleanups. * Various cleanups to our page table handling code, so we alwayse use {READ,WRITE}_ONCE. * Support for the which-cpus flavor of hwprobe. * Support for XIP kernels has been resurrected. ---------------------------------------------------------------- There will almost certainly be a part 2 next week, I've already got a few things in for-next and there's some more on the mailing lists to get through. I think the only odd thing here is that I merged in my fixes branch, which I don't usually do. I just ended up not being very productive over the holidays and missed the last few RCs, so I figured it'd be best to just merge them in rather than cherry pick them over. ---------------------------------------------------------------- Al Viro (1): use linux/export.h rather than asm-generic/export.h Alexandre Ghiti (8): riscv: Use WRITE_ONCE() when setting page table entries mm: Introduce pudp/p4dp/pgdp_get() functions riscv: mm: Only compile pgtable.c if MMU riscv: Use accessors to page table entries instead of direct dereference riscv: Check if the code to patch lies in the exit section riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping riscv: Fix module_alloc() that did not reset the linear mapping permissions riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC Andrew Jones (4): RISC-V: hwprobe: Clarify cpus size parameter RISC-V: Move the hwprobe syscall to its own file RISC-V: hwprobe: Introduce which-cpus flag RISC-V: selftests: Add which-cpus hwprobe test Ben Dooks (2): riscv: fix __user annotation in traps_misaligned.c riscv; fix __user annotation in save_v_state() Clément Léger (25): riscv: add ISA extension parsing for Zbc riscv: hwprobe: export missing Zbc ISA extension riscv: hwprobe: add support for scalar crypto ISA extensions dt-bindings: riscv: add scalar crypto ISA extensions description riscv: add ISA extension parsing for vector crypto riscv: hwprobe: export vector crypto ISA extensions dt-bindings: riscv: add vector crypto ISA extensions description riscv: add ISA extension parsing for Zfh/Zfh[min] riscv: hwprobe: export Zfh[min] ISA extensions dt-bindings: riscv: add Zfh[min] ISA extensions description riscv: add ISA extension parsing for Zihintntl riscv: hwprobe: export Zhintntl ISA extension dt-bindings: riscv: add Zihintntl ISA extension description riscv: add ISA extension parsing for Zvfh[min] riscv: hwprobe: export Zvfh[min] ISA extensions dt-bindings: riscv: add Zvfh[min] ISA extension description riscv: add ISA extension parsing for Zfa riscv: hwprobe: export Zfa ISA extension dt-bindings: riscv: add Zfa ISA extension description riscv: add ISA extension parsing for Ztso riscv: hwprobe: export Ztso ISA extension dt-bindings: riscv: add Zacas ISA extension description riscv: add ISA extension parsing for Zacas riscv: hwprobe: export Zacas ISA extension riscv: hwprobe: export Zicond extension Evan Green (1): riscv: add ISA extension parsing for scalar crypto Frederik Haxel (3): riscv: Make XIP bootable again riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro riscv: Allow disabling of BUILTIN_DTB for XIP Jisheng Zhang (1): riscv: Select ARCH_WANTS_NO_INSTR Michal Simek (1): dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible Palmer Dabbelt (8): Merge patch series "riscv: report more ISA extensions through hwprobe" Merge patch series "riscv: Use READ_ONCE()/WRITE_ONCE() for pte accesses" RISC-V: Remove the removed single-letter extensions Merge patch series "RISC-V: hwprobe: Introduce which-cpus" Merge patch series "riscv: CPU operations cleanup" Merge remote-tracking branch 'palmer/fixes' into for-next Merge patch series "Fix XIP boot and make XIP testable in QEMU" Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support" Samuel Holland (4): riscv: Deduplicate code in setup_smp() riscv: Remove unused members from struct cpu_operations riscv: Use the same CPU operations for all CPUs riscv: Remove obsolete rv32_defconfig file Song Shuai (1): riscv: Remove SHADOW_OVERFLOW_STACK_SIZE macro Documentation/arch/riscv/hwprobe.rst | 122 +++++- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/extensions.yaml | 219 +++++++++++ arch/arm/include/asm/pgtable.h | 2 + arch/riscv/Kconfig | 7 +- arch/riscv/configs/rv32_defconfig | 139 ------- arch/riscv/include/asm/cpu_ops.h | 14 +- arch/riscv/include/asm/cpufeature.h | 4 +- arch/riscv/include/asm/hwcap.h | 38 +- arch/riscv/include/asm/hwprobe.h | 24 ++ arch/riscv/include/asm/kfence.h | 4 +- arch/riscv/include/asm/pgtable-64.h | 22 +- arch/riscv/include/asm/pgtable.h | 33 +- arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/thread_info.h | 1 - arch/riscv/include/asm/xip_fixup.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 32 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 19 +- arch/riscv/kernel/cpu_ops.c | 14 +- arch/riscv/kernel/cpu_ops_sbi.c | 19 - arch/riscv/kernel/cpu_ops_spinwait.c | 11 - arch/riscv/kernel/cpufeature.c | 195 ++++++++-- arch/riscv/kernel/efi.c | 2 +- arch/riscv/kernel/head.S | 6 +- arch/riscv/kernel/mcount-dyn.S | 2 +- arch/riscv/kernel/mcount.S | 2 +- arch/riscv/kernel/module.c | 3 +- arch/riscv/kernel/patch.c | 11 +- arch/riscv/kernel/setup.c | 1 - arch/riscv/kernel/signal.c | 2 +- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/smpboot.c | 38 +- arch/riscv/kernel/sys_hwprobe.c | 411 +++++++++++++++++++++ arch/riscv/kernel/sys_riscv.c | 285 -------------- arch/riscv/kernel/traps_misaligned.c | 6 +- arch/riscv/kernel/vdso/hwprobe.c | 86 ++++- arch/riscv/kernel/vmlinux-xip.lds.S | 2 + arch/riscv/kernel/vmlinux.lds.S | 2 + arch/riscv/kvm/mmu.c | 22 +- arch/riscv/lib/clear_page.S | 2 +- arch/riscv/lib/tishift.S | 2 +- arch/riscv/lib/uaccess.S | 2 +- arch/riscv/mm/Makefile | 3 +- arch/riscv/mm/fault.c | 16 +- arch/riscv/mm/hugetlbpage.c | 12 +- arch/riscv/mm/init.c | 8 +- arch/riscv/mm/kasan_init.c | 45 +-- arch/riscv/mm/pageattr.c | 55 +-- arch/riscv/mm/pgtable.c | 51 ++- include/linux/pgtable.h | 21 ++ tools/testing/selftests/riscv/hwprobe/Makefile | 5 +- tools/testing/selftests/riscv/hwprobe/hwprobe.c | 2 +- tools/testing/selftests/riscv/hwprobe/hwprobe.h | 2 +- tools/testing/selftests/riscv/hwprobe/which-cpus.c | 154 ++++++++ .../testing/selftests/riscv/vector/vstate_prctl.c | 10 +- 56 files changed, 1471 insertions(+), 726 deletions(-) delete mode 100644 arch/riscv/configs/rv32_defconfig create mode 100644 arch/riscv/kernel/sys_hwprobe.c create mode 100644 tools/testing/selftests/riscv/hwprobe/which-cpus.c