| Message ID | mhng-e4523e07-f5ae-4f8b-9eec-8422b05700f4@palmer-ri-x1c9 (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 4a1d8ababde685a77fd4fd61e58f973cbdf29f8c |
| Headers | show |
| Series | [GIT,PULL] RISC-V Patches for the 6.15 Merge Window, Part 1 | expand |
On Fri, 4 Apr 2025 at 08:58, Palmer Dabbelt <palmer@rivosinc.com> wrote: > > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -192,10 +192,9 @@ bool arch_tlbbatch_should_defer(struct mm_struct *mm) > void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, > struct mm_struct *mm, unsigned long start, unsigned long end) > { > - unsigned long start = uaddr & PAGE_MASK; > - > cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); > - mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, start + PAGE_SIZE); > + mmu_notifier_arch_invalidate_secondary_tlbs(mm, start & PAGE_MASK, > + (end & PAGE_MASK) + PAGE_SIZE); > } That just seems wrong. All the PAGE_MASK and PAGE_SIZE games look entirely wrong and pointless. As far as I can tell, the code should just call mmu_notifier_arch_invalidate_secondary_tlbs() with the completely unmodified start and end values. They should already be page-aligned, and 'end' is already the 'one past' thing, not the final byte. And maybe I'm missing something and my resolution is wrong, but that's what I did. Somebody should obviously test it. Linus
The pull request you sent on Fri, 04 Apr 2025 08:58:06 -0700 (PDT):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.15-mw1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4a1d8ababde685a77fd4fd61e58f973cbdf29f8c
Thank you!
Hello: This pull request was applied to riscv/linux.git (fixes) by Linus Torvalds <torvalds@linux-foundation.org>: On Fri, 04 Apr 2025 08:58:06 -0700 (PDT) you wrote: > The following changes since commit 4701f33a10702d5fc577c32434eb62adde0a1ae1: > > Linux 6.14-rc7 (2025-03-16 12:55:17 -1000) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.15-mw1 > > [...] Here is the summary with links: - [GIT,PULL] RISC-V Patches for the 6.15 Merge Window, Part 1 https://git.kernel.org/riscv/c/4a1d8ababde6 You are awesome, thank you!
Hello: This pull request was applied to riscv/linux.git (for-next) by Linus Torvalds <torvalds@linux-foundation.org>: On Fri, 04 Apr 2025 08:58:06 -0700 (PDT) you wrote: > The following changes since commit 4701f33a10702d5fc577c32434eb62adde0a1ae1: > > Linux 6.14-rc7 (2025-03-16 12:55:17 -1000) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.15-mw1 > > [...] Here is the summary with links: - [GIT,PULL] RISC-V Patches for the 6.15 Merge Window, Part 1 https://git.kernel.org/riscv/c/4a1d8ababde6 You are awesome, thank you!
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index c25a40aa2fe0..c22d5eb2b185 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -192,10 +192,9 @@ bool arch_tlbbatch_should_defer(struct mm_struct *mm) void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, struct mm_struct *mm, unsigned long start, unsigned long end) { - unsigned long start = uaddr & PAGE_MASK; - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, start + PAGE_SIZE); + mmu_notifier_arch_invalidate_secondary_tlbs(mm, start & PAGE_MASK, + (end & PAGE_MASK) + PAGE_SIZE); } void arch_flush_tlb_batched_pending(struct mm_struct *mm)
The following changes since commit 4701f33a10702d5fc577c32434eb62adde0a1ae1: Linux 6.14-rc7 (2025-03-16 12:55:17 -1000) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.15-mw1 for you to fetch changes up to 3eb64093f533a29d3291a463fd65126bf430ba60: Merge tag 'riscv-mw2-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next (2025-04-03 08:53:19 -0700) ---------------------------------------------------------------- RISC-V Patches for the 6.15 Merge Window, Part 1 * The sub-architecture selection Kconfig system has been cleaned up, the documentation has been improved, and various detections have been fixed. * The vector-related extensions dependencies are now validated when parsing from device tree and in the DT bindings. * Misaligned access probing can be overridden via a kernel command-line parameter, along with various fixes to misalign access handling. * Support for relocatable !MMU kernels builds. * Support for hpge pfnmaps, which should improve TLB utilization. * Support for runtime constants, which improves the d_hash() performance. * Support for bfloat16, Zicbom, Zaamo, Zalrsc, Zicntr, Zihpm. * Various fixes, including: - We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU. - Fix ftrace panics by saving the registers as expected by ftrace. - Fix a couple of stimecmp usage related to cpu hotplug. - purgatory_start is now aligned as per the STVEC requirements. - A fix for hugetlb when calculating the size of non-present PTEs. ---------------------------------------------------------------- Unless something goes way off the rails I don't have plans for a part 2, this is very late already. Aside from that things look clean on my end. We have a pending semantic merge conflict with -next, specifically 2f4ab3ac10e1 ("mm: support tlbbatch flush for a range of PTEs") adds a new "start" parameter to arch_tlbbatch_add_pending(), while d9be2b9b60497a ("riscv: Call secondary mmu notifier when flushing the tlb") introduces a "start" local variable. Alex's suggested fix looks good to me: ---------------------------------------------------------------- Alexandre Ghiti (11): Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency" riscv: Call secondary mmu notifier when flushing the tlb Merge patch series "riscv: Add bfloat16 instruction support" Merge patch series "Support SSTC while PM operations" riscv: Fix missing __free_pages() in check_vector_unaligned_access() Merge patch series "riscv: add support for Zaamo and Zalrsc extensions" Merge patch series "riscv: Unaligned access speed probing fixes and skipping" Merge patch series "riscv: Add runtime constant support" riscv: Fix hugetlb retrieval of number of ptes in case of !present pte Merge patch series "Add some validation for vector, vector crypto and fp stuff" riscv: Make sure toolchain supports zba before using zba instructions Andrew Bresticker (1): riscv: Support huge pfnmaps Andrew Jones (8): riscv: Annotate unaligned access init functions riscv: Fix riscv_online_cpu_vec riscv: Fix check_unaligned_access_all_cpus riscv: Change check_unaligned_access_speed_all_cpus to void riscv: Fix set up of cpu hotplug callbacks riscv: Fix set up of vector cpu hotplug callback riscv: Add parameter for skipping access speed tests Documentation/kernel-parameters: Add riscv unaligned speed parameters Björn Töpel (1): riscv/purgatory: 4B align purgatory_start Charlie Jenkins (5): riscv: tracing: Fix __write_overflow_field in ftrace_partial_regs() riscv: Move nop definition to insn-def.h riscv: Add runtime constant support riscv: Add norvc after .option arch in runtime const riscv: Add norvc after .option arch in runtime const Chin Yik Ming (2): riscv: Simplify base extension checks and direct boolean return riscv: Fix a comment typo in set_mm_asid() Clément Léger (6): riscv: remove useless pc check in stacktrace handling dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description riscv: add parsing for Zaamo and Zalrsc extensions riscv: hwprobe: export Zaamo and Zalrsc extensions RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test Conor Dooley (8): RISC-V: clarify what some RISCV_ISA* config options do RISC-V: separate Zbb optimisations requiring and not requiring toolchain support RISC-V: add vector extension validation checks RISC-V: add vector crypto extension validation checks RISC-V: add f & d extension validation checks dt-bindings: riscv: d requires f dt-bindings: riscv: add vector sub-extension dependencies dt-bindings: riscv: document vector crypto requirements Geert Uytterhoeven (2): riscv: defconfig: Disable Renesas SoC support riscv: Remove duplicate CLINT_TIMER selections Guo Ren (1): riscv: Implement smp_cond_load8/16() with Zawrs Ignacio Encinas (1): selftests: riscv: fix v_exec_initval_nolibc.c Inochi Amaoto (3): dt-bindings: riscv: add bfloat16 ISA extension description riscv: add ISA extension parsing for bfloat16 ISA extension riscv: hwprobe: export bfloat16 ISA extension Jinjie Ruan (1): riscv: Remove unused TASK_TI_FLAGS Juhan Jin (1): riscv: ftrace: Add parentheses in macro definitions of make_call_t0 and make_call_ra Masahiro Yamada (1): riscv: migrate to the generic rule for built-in DTB Miquel Sabaté Solà (1): riscv: hwprobe: export Zicntr and Zihpm extensions Nick Hu (2): riscv: Add stimecmp save and restore clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug Palmer Dabbelt (4): Merge tag 'riscv-mw1-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next RISC-V: errata: Use medany for relocatable builds Merge patch series "riscv: Relocatable NOMMU kernels" Merge tag 'riscv-mw2-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next Pu Lehui (2): riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler Samuel Holland (6): riscv: Remove duplicate CONFIG_PAGE_OFFSET definition riscv: Allow NOMMU kernels to access all of RAM riscv: Support CONFIG_RELOCATABLE on NOMMU asm-generic: Always define Elf_Rel and Elf_Rela riscv: Support CONFIG_RELOCATABLE on riscv32 riscv: Remove CONFIG_PAGE_OFFSET Thomas Weißschuh (1): riscv: mm: Don't use %pK through printk Tingbo Liao (1): riscv: Fix the __riscv_copy_vec_words_unaligned implementation Yao Zi (1): riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator Yunhui Cui (4): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests riscv: print hartid on bringup Zixian Zeng (1): riscv: remove redundant CMDLINE_FORCE check Documentation/admin-guide/kernel-parameters.txt | 16 ++ Documentation/arch/riscv/hwprobe.rst | 32 +++ .../devicetree/bindings/riscv/extensions.yaml | 149 ++++++++++++ arch/riscv/Kbuild | 1 - arch/riscv/Kconfig | 84 ++++--- arch/riscv/Kconfig.socs | 2 - arch/riscv/Makefile | 1 - arch/riscv/boot/dts/Makefile | 2 - arch/riscv/configs/defconfig | 2 - arch/riscv/configs/nommu_k210_defconfig | 2 +- arch/riscv/configs/nommu_k210_sdcard_defconfig | 2 +- arch/riscv/errata/Makefile | 6 +- arch/riscv/include/asm/arch_hweight.h | 6 +- arch/riscv/include/asm/asm.h | 1 + arch/riscv/include/asm/bitops.h | 4 +- arch/riscv/include/asm/checksum.h | 3 +- arch/riscv/include/asm/cmpxchg.h | 38 ++- arch/riscv/include/asm/cpufeature.h | 7 +- arch/riscv/include/asm/ftrace.h | 7 +- arch/riscv/include/asm/hwcap.h | 5 + arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/insn-def.h | 3 + arch/riscv/include/asm/page.h | 27 +-- arch/riscv/include/asm/pgtable.h | 55 ++++- arch/riscv/include/asm/ptrace.h | 18 +- arch/riscv/include/asm/runtime-const.h | 268 +++++++++++++++++++++ arch/riscv/include/asm/suspend.h | 4 + arch/riscv/include/uapi/asm/hwprobe.h | 9 + arch/riscv/include/uapi/asm/kvm.h | 2 + arch/riscv/kernel/asm-offsets.c | 1 - arch/riscv/kernel/cpufeature.c | 197 +++++++++++---- arch/riscv/kernel/elf_kexec.c | 3 + arch/riscv/kernel/ftrace.c | 6 +- arch/riscv/kernel/jump_label.c | 4 +- arch/riscv/kernel/mcount.S | 24 +- arch/riscv/kernel/setup.c | 5 - arch/riscv/kernel/smp.c | 2 + arch/riscv/kernel/smpboot.c | 4 + arch/riscv/kernel/stacktrace.c | 2 +- arch/riscv/kernel/suspend.c | 14 ++ arch/riscv/kernel/sys_hwprobe.c | 15 +- arch/riscv/kernel/traps_misaligned.c | 14 +- arch/riscv/kernel/unaligned_access_speed.c | 242 ++++++++++++------- arch/riscv/kernel/vec-copy-unaligned.S | 2 +- arch/riscv/kernel/vendor_extensions.c | 2 +- arch/riscv/kernel/vmlinux.lds.S | 3 + arch/riscv/kvm/vcpu_onereg.c | 4 + arch/riscv/lib/csum.c | 21 +- arch/riscv/lib/strcmp.S | 5 +- arch/riscv/lib/strlen.S | 5 +- arch/riscv/lib/strncmp.S | 5 +- arch/riscv/mm/context.c | 2 +- arch/riscv/mm/hugetlbpage.c | 76 +++--- arch/riscv/mm/init.c | 97 ++++---- arch/riscv/mm/physaddr.c | 2 +- arch/riscv/mm/tlbflush.c | 37 +-- arch/riscv/purgatory/entry.S | 1 + drivers/clocksource/timer-riscv.c | 6 + include/asm-generic/module.h | 8 - tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 + tools/testing/selftests/riscv/hwprobe/cbo.c | 66 ++++- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 10 +- 62 files changed, 1252 insertions(+), 399 deletions(-) create mode 100644 arch/riscv/include/asm/runtime-const.h