| Message ID | mhng-ff3fd3dc-81e2-440e-9e77-b97a64e23520@palmer-ri-x1c9 (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [GIT,PULL] RISC-V Patches for the 6.7 Merge Window, Part 1 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
The pull request you sent on Mon, 06 Nov 2023 07:13:47 -0800 (PST):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.7-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d46392bbf5c6ce594669f00b8177f0b34e983f90
Thank you!
The following changes since commit 8eb8fe67e2c84324398f5983c41b4f831d0705b3: riscv: errata: fix T-Head dcache.cva encoding (2023-09-12 13:58:40 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.7-rc1 for you to fetch changes up to e1c05b3bf80f829ced464bdca90f1dfa96e8d251: RISC-V: hwprobe: Fix vDSO SIGSEGV (2023-11-02 14:05:30 -0700) ---------------------------------------------------------------- RISC-V Patches for the 6.7 Merge Window, Part 1 * Support for cbo.zero in userspace. * Support for CBOs on ACPI-based systems. * A handful of improvements for the T-Head cache flushing ops. * Support for software shadow call stacks. * Various cleanups and fixes. ---------------------------------------------------------------- I have two manually resolved merge conflicts. There's one in csr.h, which is just a list of CSR numbers. There's also one in irq.c, which is the result of a fix conflicting with some new functionality. Here's my resolution, see 07a27665754b ("RISC-V: Fix wrong use of CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK"): --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@@ -60,41 -79,23 +79,23 @@@ static void init_irq_stacks(void } #endif /* CONFIG_VMAP_STACK */ -#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK +#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK + static void ___do_softirq(struct pt_regs *regs) + { + __do_softirq(); + } I'll almost certainly have more for later this week, there's already some on for-next that I wanted to give a little more time for testing. ---------------------------------------------------------------- Andrew Jones (7): RISC-V: Make zicbom/zicboz errors consistent RISC-V: Enable cbo.zero in usermode RISC-V: hwprobe: Expose Zicboz extension and its block size RISC-V: selftests: Statically link hwprobe test RISC-V: selftests: Convert hwprobe test to kselftest API RISC-V: selftests: Add CBO tests RISC-V: hwprobe: Fix vDSO SIGSEGV Anup Patel (2): clocksource: timer-riscv: Don't enable/disable timer interrupt clocksource: timer-riscv: Increase rating of clock_event_device for Sstc Deepak Gupta (1): riscv: VMAP_STACK overflow detection thread-safe Icenowy Zheng (1): riscv: errata: prefix T-Head mnemonics with th. Lad Prabhakar (1): riscv: configs: defconfig: Enable configs required for RZ/Five SoC Minda Chen (1): riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause Nam Cao (1): riscv: put interrupt entries into .irqentry.text Palmer Dabbelt (6): Merge patch series "riscv: kexec: cleanup and fixups" Merge patch series "RISC-V: Enable cbo.zero in usermode" RISC-V: Provide pgtable_l5_enabled on rv32 Merge patch series "RISC-V: ACPI improvements" Merge patch "riscv: errata: improve T-Head CMO" Merge patch series "riscv: SCS support" Sami Tolvanen (5): riscv: Deduplicate IRQ stack switching riscv: Move global pointer loading to a macro riscv: Implement Shadow Call Stack riscv: Use separate IRQ shadow call stacks lkdtm: Fix CFI_BACKWARD on RISC-V Song Shuai (5): riscv: kexec: Cleanup riscv_kexec_relocate riscv: kexec: Align the kexeced kernel entry riscv: kexec: Remove -fPIE for PURGATORY_CFLAGS riscv: correct pt_level name via pgtable_l5/4_enabled riscv: mm: Update the comment of CONFIG_PAGE_OFFSET Sunil V L (4): RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping RISC-V: ACPI: Update the return value of acpi_get_rhct() RISC-V: ACPI: RHCT: Add function to get CBO block sizes RISC-V: cacheflush: Initialize CBO variables on ACPI systems Tsukasa OI (1): RISC-V: clarify the QEMU workaround in ISA parser Xiao Wang (1): riscv/mm: Fix the comment for swap pte format Documentation/riscv/hwprobe.rst | 6 + arch/riscv/Kconfig | 7 + arch/riscv/Makefile | 4 + arch/riscv/configs/defconfig | 52 ++++++ arch/riscv/include/asm/acpi.h | 6 + arch/riscv/include/asm/asm-prototypes.h | 1 - arch/riscv/include/asm/asm.h | 41 +++++ arch/riscv/include/asm/cpufeature.h | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/errata_list.h | 14 +- arch/riscv/include/asm/hwcap.h | 16 ++ arch/riscv/include/asm/hwprobe.h | 7 +- arch/riscv/include/asm/irq_stack.h | 3 + arch/riscv/include/asm/page.h | 4 +- arch/riscv/include/asm/pgtable-32.h | 3 + arch/riscv/include/asm/pgtable.h | 3 +- arch/riscv/include/asm/scs.h | 54 ++++++ arch/riscv/include/asm/thread_info.h | 16 +- arch/riscv/include/asm/vdso/processor.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/acpi.c | 87 ++++++++- arch/riscv/kernel/asm-offsets.c | 9 + arch/riscv/kernel/cpufeature.c | 17 +- arch/riscv/kernel/entry.S | 126 +++++++------ arch/riscv/kernel/head.S | 19 +- arch/riscv/kernel/irq.c | 56 +++--- arch/riscv/kernel/kexec_relocate.S | 52 +++--- arch/riscv/kernel/setup.c | 4 + arch/riscv/kernel/smpboot.c | 4 + arch/riscv/kernel/suspend_entry.S | 5 +- arch/riscv/kernel/sys_riscv.c | 46 +++-- arch/riscv/kernel/traps.c | 68 +------ arch/riscv/kernel/vdso/Makefile | 2 +- arch/riscv/kernel/vdso/hwprobe.c | 2 +- arch/riscv/mm/cacheflush.c | 25 ++- arch/riscv/mm/init.c | 2 + arch/riscv/mm/ptdump.c | 3 + arch/riscv/purgatory/Makefile | 8 + drivers/acpi/riscv/rhct.c | 93 +++++++++- drivers/clocksource/timer-riscv.c | 17 +- drivers/misc/lkdtm/cfi.c | 13 +- tools/testing/selftests/riscv/hwprobe/Makefile | 9 +- tools/testing/selftests/riscv/hwprobe/cbo.c | 228 ++++++++++++++++++++++++ tools/testing/selftests/riscv/hwprobe/hwprobe.c | 64 +++---- tools/testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++ 45 files changed, 919 insertions(+), 298 deletions(-) create mode 100644 arch/riscv/include/asm/scs.h create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h