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[76.244.6.13]) by smtp.gmail.com with ESMTPSA id i21-20020a9d68d5000000b00639749ef262sm3385355oto.9.2022.09.12.13.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 13:56:11 -0700 (PDT) From: Chris Morgan To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-phy@lists.infradead.org, cl@rock-chips.com, s.hauer@pengutronix.de, frattaroli.nicolas@gmail.com, michael.riesch@wolfvision.net, pgwipeout@gmail.com, heiko@sntech.de, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, vkoul@kernel.org, kishon@ti.com, Chris Morgan Subject: [PATCH v3 0/3] rockchip-dsi for rk3568 Date: Mon, 12 Sep 2022 15:56:04 -0500 Message-Id: <20220912205607.5969-1-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220912_135613_554396_82CD3A33 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Chris Morgan This series adds support for the dsi and dphy controllers on the Rockchip RK3568. Tested on an Anbernic RG503, Anbernic RG353P, and Odroid Go Advance. Changes since V2: - Removed dsi controller patches, as those have been merged upstream. - Removed notes about rolling back clock drivers. If I set the parent clock of the VOP port I'm using to VPLL and set the clock rate of PLL_VPLL to 500MHz this series works correctly for my panels without rolling anything back (per Heiko this is the correct way). - Added additional details about refactoring DPHY driver to add 2.5GHz for rk356x. All other devices still have a max speed of 1GHz. - Notified Heiko that the BIT(5) for both PLL_POST_DIV_ENABLE and PLL_POST_DIV_ENABLE_MASK is deliberate, because of how the phy_update_bits() works. Changes since RFCv1: - Identified cause of image shift (clock changes). - Noted that driver works now. - Added devicetree nodes for rk356x.dtsi. Chris Morgan (3): dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568 phy/rockchip: inno-dsidphy: Add support for rk3568 arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 72 +++++++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++++++++++++++---- 3 files changed, 231 insertions(+), 46 deletions(-) Tested-by: Michael Riesch