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AJvYcCX4QZueLdx3KN7In3MfAZwSsT6lmSlAnNXTfqJKbdEdrKoZHg6JNPhqqiNEhfGOjyQDzxl4TdbfazIFV8YpYwUMQ+fwtqyS2sqyqYfRRJGcmLWI+FwpkEypQxdPlLru10JlaxEJSgD44pkBHU8jY0QD3+/f5qBlxTw= X-Gm-Message-State: AOJu0YytCI+PpRAr6fhzFoi/iTEFcBLfAVX5l74Kzwruju8pPToxCh+i VFYIQcPTWZIAB/nzVnkitL0Iij9kM7e5BUn1TK1DJyrsIl1av8TJ X-Google-Smtp-Source: AGHT+IG4Hkq6991vIoxDDRYmbp1gvzhu/qj+0mxidX62jQ3RMGCze6F96qvW6K5C207sigpd1tp2RQ== X-Received: by 2002:a05:6512:124d:b0:516:cf23:588 with SMTP id 2adb3069b0e04-5220fc7bef6mr16714600e87.27.1715775464345; Wed, 15 May 2024 05:17:44 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f35ad684sm2515614e87.3.2024.05.15.05.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 05:17:44 -0700 (PDT) From: Dmitry Yashin To: Linus Walleij , Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley , Rob Herring Cc: Luca Ceresoli , Jianqun Xu , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH 0/3] pinctrl: rockchip: add rk3308b SoC support Date: Wed, 15 May 2024 17:16:31 +0500 Message-ID: <20240515121634.23945-1-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.45.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_051754_391365_68B98A90 X-CRM114-Status: GOOD ( 10.34 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org This patch series fixes iomux routes on rk3308 and adds support for pin controller found on rk3308b. According to rk3308b TRM, this pinctrl much the same as rk3308's, but with additional iomux routes and 3bit iomuxes selected via gpio##_sel_src_ctrl registers. Downstream kernel [1] managed this SoC's with rk3308b_soc_data_init, wich picked configuration based on cpuid. Upstream pinctrl patches droped soc init function. The function rk3308b_soc_sel_src_init sets up gpio##_sel_src_ctrl registers, making SoC to use 3bit iomuxes over some 2bit old ones. These patches have been tested on Radxa's ROCK Pi S, one based on rk3308 and the other on rk3308b (from the latest batches). For the new boards fixes broken spi1 clk. Similar effort [2] was made several years ago, but without keeping base rk3308 SoC pinctrl support. [1] https://github.com/radxa/kernel/blob/stable-4.4-rockpis/drivers/pinctrl/pinctrl-rockchip.c#L4388 [2] https://lore.kernel.org/linux-rockchip/20220930102620.1568864-1-jay.xu@rock-chips.com/ Dmitry Yashin (3): pinctrl: rockchip: update rk3308 iomux routes dt-bindings: pinctrl: rockchip: add rk3308b pinctrl: rockchip: add rk3308b SoC support .../bindings/pinctrl/rockchip,pinctrl.yaml | 1 + drivers/pinctrl/pinctrl-rockchip.c | 187 ++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 1 + 3 files changed, 189 insertions(+) base-commit: ed30a4a51bb196781c8058073ea720133a65596f