[v10,0/3] Add initial support for the Rockchip RK3588 HDMI TX Controller

Message

Cristian Ciocaltea Oct. 16, 2024, 8:06 p.m. UTC

The Rockchip RK3588 SoC family integrates the Synopsys DesignWare HDMI
2.1 Quad-Pixel (QP) TX controller, which is a new IP block, quite
different from those used in the previous generations of Rockchip SoCs.

The controller supports the following features, among others:

* Fixed Rate Link (FRL)
* Display Stream Compression (DSC)
* 4K@120Hz and 8K@60Hz video modes
* Variable Refresh Rate (VRR) including Quick Media Switching (QMS)
* Fast Vactive (FVA)
* SCDC I2C DDC access
* Multi-stream audio
* Enhanced Audio Return Channel (EARC)

This is the last component that needs to be supported in order to enable
the HDMI output functionality on the RK3588 based SBCs, such as the
RADXA Rock 5B.  The other components are the Video Output Processor
(VOP2) and the Samsung IP based HDMI/eDP TX Combo PHY, for which basic
support has been already made available via [1] and [2], respectively.

Please note this is a reworked version of the original series, which
relied on a commonized dw-hdmi approach.  Since the general consensus
was to handle it as an entirely new IP, I dropped all patches related to
the old dw-hdmi and Rockchip glue code - a few of them might still make
sense as general improvements and will be submitted separately.

It's worth mentioning the HDMI output support is currently limited to
RGB output up to 4K@60Hz, without audio, CEC or any of the HDMI 2.1
specific features.  Moreover, the VOP2 driver is not able to properly
handle all display modes supported by the connected screens, e.g. it
doesn't cope with non-integer refresh rates.

A possible workaround consists of enabling the display controller to
make use of the clock provided by the HDMI PHY PLL.  This is still work
in progress and will be submitted later, as well as the required DTS
updates.

To facilitate testing and experimentation, all HDMI output related
patches, including those part of this series, are available at [3].

So far I could only verify this on the RADXA Rock 5B board.

Thanks,
Cristian

[1]: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
[2]: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
[3]: https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-hdmi-bridge-v6.12-rc2
[4]: https://lore.kernel.org/lkml/[e-mail]/

Signed-off-by: Cristian Ciocaltea <[e-mail]>
---
Changes in v10:
- Used the .remove() callback instead of .remove_new() and dropped the
  superfluous white space after .probe assignment (Uwe)
- Link to v9: https://lore.kernel.org/r/[e-mail]

Changes in v9:
- Introduced HOTPLUG_DEBOUNCE_MS constant and used it for both HPD
  high/low IRQs handling (Jonas)
- Made use of drm_hdmi_compute_mode_clock() instead of assuming TMDS
  character rate does always match pixel clock (Maxime)
- Collected R-b tags from Maxime
- Rebased series onto v6.12-rc2
- Link to v8: https://lore.kernel.org/r/[e-mail]

Changes in v8:
- Added R-b tag from Maxime on the HDMI controller library patch
- Dropped dw_hdmi_qp_rockchip_encoder_mode_set() from the platform
  driver according to Maxime's review, the ref_clk rate adjustment is
  already handled in dw_hdmi_qp_rockchip_encoder_enable()
- Link to v7: https://lore.kernel.org/r/[e-mail]

Changes in v7:
- Added R-b from Krzysztof on DT binding patch (also dropped the
  superfluous minItems property from resets)
- Fixed a sparse warning reported by kernel test robot when returning
  the error pointer from devm_platform_ioremap_resource() (made use of
  ERR_CAST() helper)
- Simplified locking in dw_hdmi_qp_i2c_xfer() via guard() (Markus)
- Dropped high TMDS clock ratio and scrambling support for now (will be
  submitted separately when ready)
- Introduced dw_hdmi_qp_bridge_mode_valid() function to filter out
  unsupported mode clocks
- Dropped the superfluous 'display' parameter of ->init() in struct
  dw_hdmi_qp_phy_ops
- Improved error handling in dw_hdmi_qp_bridge_atomic_enable()
- Handled dw_hdmi_qp_i2c_adapter() errors as fatal for bridge setup
- Rebased series onto next-20240913
- Updated ROCKCHIP_DW_HDMI_QP kconfig to select the recently introduced
  DRM_BRIDGE_CONNECTOR dependency (Heiko)
- Link to v6: https://lore.kernel.org/r/[e-mail]

Changes in v6:
- Improved scrambling setup by using a delayed work queue in conjunction
  with the bridge ->detect() callback to support use cases like modetest
  where ->atomic_enable() is not called on reconnection (Maxime)
- Explicitly include workqueue.h in platform driver
- Dropped the common binding patch after merging its content into RK
  specific one; also moved the clocks & irq setup from the bridge
  library to the platform driver
- Got rid of the phy-names property and fixed indentation in the binding
  example (Krzysztof)
- Link to v5: https://lore.kernel.org/r/[e-mail]

Changes in v5:
- Renamed Rockchip binding file to match the SoC compatible (Conor)
- Made all clocks mandatory (Conor)
- Renamed rockchip,vo1-grf property to rockchip,vo-grf as future SoCs
  (e.g. RK3576) may refer to it as vo0 instead of vo1
- Reworked the setup of high TMDS clock ratio and scrambling
  * Dropped curr_conn & pix_clock from struct dw_hdmi_qp
  * Also removed exported function dw_hdmi_qp_set_high_tmds_clock_ratio()
  * A few additional (mostly cosmetic) changes
- Link to v4: https://lore.kernel.org/r/[e-mail]

Changes in v4:
- Added Tested-by tag from Heiko
- Updated "[PATCH v3 3/5] dt-bindings: display: rockchip: Add schema for
  RK3588 HDMI TX Controller" according to Rob's review
  * Referenced full path for synopsys,dw-hdmi-qp.yaml
  * Moved ports to common schema and updated descriptions
  * Renamed rockchip,vo1_grf to rockchip,vo1-grf and updated "[PATCH v3
    5/5] drm/rockchip: Add basic RK3588 HDMI output support" accordingly
- Dropped "[PATCH v3 4/5] drm/rockchip: Explicitly include bits header"
  already applied by Heiko
- Link to v3: https://lore.kernel.org/r/[e-mail]

Changes in v3:
- Reintegrated bridge patchset [4] to allow automated testing and
  simplify reviewing (Krzysztof); the after-split changes were:
  * Made use of the new bridge HDMI helpers indicated by Dmitry
  * Dropped connector creation to ensure driver does only support
    DRM_BRIDGE_ATTACH_NO_CONNECTOR
  * Updated I2C segment handling to properly handle connected DVI
    displays (reported and fixed by Heiko)
- Updated schema for DW HDMI QP TX IP providing some hardware details
- Updated patch for DW HDMI QP TX Controller module referring to a
  support library instead of a platform driver (Krzysztof)
- Drop empty dw_hdmi_qp_unbind() export from the library and related
  usage from RK platform driver
- Drop Fixes tag from "drm/rockchip: Explicitly include bits header"
  patch (Krzysztof)
- Link to v2: https://lore.kernel.org/r/[e-mail]

Changes in v2:
- Reworked the glue code for RK3588 into a new Rockchip platform driver
- Moved bridge driver patches to a separate series [4]
- Dropped all the patches touching to the old dw-hdmi and RK platform
  drivers
- Added connector creation to ensure the HDMI QP bridge driver does only
  support DRM_BRIDGE_ATTACH_NO_CONNECTOR
- Link to v1: https://lore.kernel.org/r/[e-mail]

---
Cristian Ciocaltea (3):
      drm/bridge: synopsys: Add DW HDMI QP TX Controller support library
      dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller
      drm/rockchip: Add basic RK3588 HDMI output support

 .../rockchip/rockchip,rk3588-dw-hdmi-qp.yaml       | 188 +++++
 drivers/gpu/drm/bridge/synopsys/Kconfig            |   8 +
 drivers/gpu/drm/bridge/synopsys/Makefile           |   2 +
 drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c       | 647 ++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h       | 834 +++++++++++++++++++++
 drivers/gpu/drm/rockchip/Kconfig                   |   9 +
 drivers/gpu/drm/rockchip/Makefile                  |   1 +
 drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c     | 424 +++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c        |   2 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |   1 +
 include/drm/bridge/dw_hdmi_qp.h                    |  32 +
 11 files changed, 2148 insertions(+)
---
base-commit: 8cf0b93919e13d1e8d4466eb4080a4c4d9d66d7b
change-id: 20240601-b4-rk3588-bridge-upstream-a27baff1b8fc

Comments

Maxime Ripard Oct. 17, 2024, 2:11 p.m. UTC | #1

On Wed, 16 Oct 2024 23:06:50 +0300, Cristian Ciocaltea wrote:
> The Rockchip RK3588 SoC family integrates the Synopsys DesignWare HDMI
> 2.1 Quad-Pixel (QP) TX controller, which is a new IP block, quite
> different from those used in the previous generations of Rockchip SoCs.
> 
> The controller supports the following features, among others:
> 
> * Fixed Rate Link (FRL)
> * Display Stream Compression (DSC)
> * 4K@120Hz and 8K@60Hz video modes
> * Variable Refresh Rate (VRR) including Quick Media Switching (QMS)
> * Fast Vactive (FVA)
> * SCDC I2C DDC access
> * Multi-stream audio
> * Enhanced Audio Return Channel (EARC)
> 
> [...]

Applied to misc/kernel.git (drm-misc-next).

Thanks!
Maxime