| Message ID | 20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58@collabora.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Improve Rockchip VOP2 display modes handling on RK3588 HDMI0 | expand |
On Tue, 04 Feb 2025 14:40:03 +0200, Cristian Ciocaltea wrote: > VOP2 support for RK3588 SoC is currently not capable to handle the full > range of display modes advertised by the connected screens, e.g. it > doesn't cope well with non-integer refresh rates like 59.94, 29.97, > 23.98, etc. > > There are two HDMI PHYs available on RK3588, each providing a PLL that > can be used by three out of the four VOP2 video ports as an alternative > and more accurate pixel clock source. They are able to handle display > modes up to 4K@60Hz, anything above that, e.g. the maximum supported > 8K@60Hz resolution, is supposed to be handled by the system CRU. > > [...] Applied, thanks! [1/5] dt-bindings: display: vop2: Add optional PLL clock properties commit: 79982cbac896768c3860c241df2028c3e75f5a6b [2/5] drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation commit: 9f40d7a94427a503e303b2a2d8db227d615e32c1 [3/5] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0 commit: 2c1268e7aad0819f38e56134bbc2095fd95fde1b Best regards,
On Tue, 04 Feb 2025 14:40:03 +0200, Cristian Ciocaltea wrote: > VOP2 support for RK3588 SoC is currently not capable to handle the full > range of display modes advertised by the connected screens, e.g. it > doesn't cope well with non-integer refresh rates like 59.94, 29.97, > 23.98, etc. > > There are two HDMI PHYs available on RK3588, each providing a PLL that > can be used by three out of the four VOP2 video ports as an alternative > and more accurate pixel clock source. They are able to handle display > modes up to 4K@60Hz, anything above that, e.g. the maximum supported > 8K@60Hz resolution, is supposed to be handled by the system CRU. > > [...] Applied, thanks! [4/5] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 commit: d0f17738778c12be629ba77ff00c43c3e9eb8428 [5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588 commit: eb4262203d7d85eb7b6f2696816db272e41f5464 Best regards,
VOP2 support for RK3588 SoC is currently not capable to handle the full range of display modes advertised by the connected screens, e.g. it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. There are two HDMI PHYs available on RK3588, each providing a PLL that can be used by three out of the four VOP2 video ports as an alternative and more accurate pixel clock source. They are able to handle display modes up to 4K@60Hz, anything above that, e.g. the maximum supported 8K@60Hz resolution, is supposed to be handled by the system CRU. There is quite a bit of complexity in downstream driver to handle all possible usecases - see [1] for a brief description on how was that designed to work. As for the moment HDMI1 output support [2] is not fully merged upstream, the patch series targets HDMI0 only. Additionally, please note that testing any HDMI 2.0 specific modes, e.g. 4K@60Hz, requires high TMDS clock ratio and scrambling capability [3]. Thanks, Cristian [1] https://github.com/radxa/kernel/blob/linux-6.1-stan-rkr4.1/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c#L4742 [2] https://lore.kernel.org/lkml/20241211-rk3588-hdmi1-v2-0-02cdca22ff68@collabora.com/ [3] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-hdmi-bridge-v6.14-rc1 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> --- Changes in v3: - Check the already computed clock instead of mode->crtc_clock in the conditional that triggers the switch to HDMI PHY PLL - Rebased series onto v6.14-rc1 - Link to v2: https://lore.kernel.org/r/20241211-vop2-hdmi0-disp-modes-v2-0-471cf5001e45@collabora.com Changes in v2: - Collected Acked-by tag from Rob and Tested-by from Naoki - Rebased series onto v6.13-rc1 - Link to v1: https://lore.kernel.org/r/20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com --- Cristian Ciocaltea (5): dt-bindings: display: vop2: Add optional PLL clock properties drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0 arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588 .../bindings/display/rockchip/rockchip-vop2.yaml | 4 +++ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 7 +++-- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 36 +++++++++++++++++++++- 3 files changed, 44 insertions(+), 3 deletions(-) --- base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b change-id: 20241116-vop2-hdmi0-disp-modes-b39e3619768f