diff mbox series

[v2,8/8] ARM: dts: rockchip: rk3066a: move gpio nodes to root

Message ID 0266aabd-2991-2958-ab1e-55f58ab14461@gmail.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/8] dt-bindings: gpio: rockchip,gpio-bank: add compatible string per SoC | expand

Commit Message

Johan Jonker Jan. 21, 2023, 11:10 a.m. UTC 
The relation between gpio and pinctrl is now described
by the gpio-ranges property. Move rk3066a gpio nodes to root.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 arch/arm/boot/dts/rk3066a.dtsi | 159 +++++++++++++++------------------
 1 file changed, 72 insertions(+), 87 deletions(-)

--
2.20.1
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4d7cf6f1b..ac329cf14 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -217,6 +217,18 @@ 
 				       <150000000>, <75000000>;
 	};

+	gpio6: gpio@2000a000 {
+		compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+		reg = <0x2000a000 0x100>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO6>;
+		gpio-controller;
+		gpio-ranges = <&pinctrl 0 192 32>;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	timer2: timer@2000e000 {
 		compatible = "snps,dw-apb-timer";
 		reg = <0x2000e000 0x100>;
@@ -238,6 +250,18 @@ 
 		};
 	};

+	gpio0: gpio@20034000 {
+		compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+		reg = <0x20034000 0x100>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO0>;
+		gpio-controller;
+		gpio-ranges = <&pinctrl 0 0 32>;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	timer0: timer@20038000 {
 		compatible = "snps,dw-apb-timer";
 		reg = <0x20038000 0x100>;
@@ -254,6 +278,30 @@ 
 		clock-names = "timer", "pclk";
 	};

+	gpio1: gpio@2003c000 {
+		compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+		reg = <0x2003c000 0x100>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO1>;
+		gpio-controller;
+		gpio-ranges = <&pinctrl 0 32 32>;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio@2003e000 {
+		compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+		reg = <0x2003e000 0x100>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO2>;
+		gpio-controller;
+		gpio-ranges = <&pinctrl 0 64 32>;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	tsadc: tsadc@20060000 {
 		compatible = "rockchip,rk3066-tsadc";
 		reg = <0x20060000 0x100>;
@@ -266,96 +314,33 @@ 
 		status = "disabled";
 	};

+	gpio3: gpio@20080000 {
+		compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+		reg = <0x20080000 0x100>;
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO3>;
+		gpio-controller;
+		gpio-ranges = <&pinctrl 0 96 32>;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio4: gpio@20084000 {
+		compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+		reg = <0x20084000 0x100>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO4>;
+		gpio-controller;
+		gpio-ranges = <&pinctrl 0 128 32>;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3066a-pinctrl";
 		rockchip,grf = <&grf>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		gpio0: gpio@20034000 {
-			compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
-			reg = <0x20034000 0x100>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO0>;
-
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 0 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio@2003c000 {
-			compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
-			reg = <0x2003c000 0x100>;
-			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>;
-
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 32 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@2003e000 {
-			compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
-			reg = <0x2003e000 0x100>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>;
-
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 64 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@20080000 {
-			compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
-			reg = <0x20080000 0x100>;
-			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>;
-
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 96 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio4: gpio@20084000 {
-			compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
-			reg = <0x20084000 0x100>;
-			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO4>;
-
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 128 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio6: gpio@2000a000 {
-			compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
-			reg = <0x2000a000 0x100>;
-			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO6>;
-
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 192 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};

 		pcfg_pull_default: pcfg-pull-default {
 			bias-pull-pin-default;