From patchwork Tue Sep 16 10:44:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 4916241 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 156C09F466 for ; Tue, 16 Sep 2014 10:45:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AD3E6201CE for ; Tue, 16 Sep 2014 10:47:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72A43201BF for ; Tue, 16 Sep 2014 10:47:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XTqIT-0006Ze-2i; Tue, 16 Sep 2014 10:47:45 +0000 Received: from mail-pa0-x233.google.com ([2607:f8b0:400e:c03::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XTqII-0006MQ-Dv; Tue, 16 Sep 2014 10:47:35 +0000 Received: by mail-pa0-f51.google.com with SMTP id kx10so8565473pab.24 for ; Tue, 16 Sep 2014 03:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=12snHojvqrDATO4krk+6Qn79fQRegFZzP2TII0tyEBA=; b=ammZ52r1Y2NsIQboYtWKYOQD4GApdPZ+LPphB8tUOCH0FF8jhln4JGwQpTBsKNYmGe LhAtK+45ws08S/gw2ykJJSAemfimHUqihmGgBwyrs4zYC85unrihMZ9qmqiLsqT68xQG T+YBSLdOE0ul6vX534s7aqWvxgYqfn/tcvz7MLPRKtO93Y80kZahHYbSs2VMG17QTeQB LjcLVur//ZoMJCQjzgFn6pf6eq+XnZBP4Fh6k9Q0/nvayEvKPP+WeK+2qfcMHWR7tliO Tib5aNl4U3pADyIKn9Lu8r1V6BpcAjuziSXSXL2sIt4ZX4MVW/3Hy+Oc9e8gNibci2ZU hg4A== X-Received: by 10.67.12.175 with SMTP id er15mr14672815pad.143.1410864433216; Tue, 16 Sep 2014 03:47:13 -0700 (PDT) Received: from localhost.localdomain ([58.22.7.114]) by mx.google.com with ESMTPSA id fk11sm13749455pdb.91.2014.09.16.03.47.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 Sep 2014 03:47:12 -0700 (PDT) From: Kever Yang To: heiko@sntech.de Subject: [PATCH v2 2/3] ARM: rockchip: add basic smp support for rk3288 Date: Tue, 16 Sep 2014 18:44:29 +0800 Message-Id: <1410864271-9277-3-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1410864271-9277-1-git-send-email-kever.yang@rock-chips.com> References: <1410864271-9277-1-git-send-email-kever.yang@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140916_034734_522851_F50657BB X-CRM114-Status: GOOD ( 16.16 ) X-Spam-Score: -0.7 (/) Cc: huangtao@rock-chips.com, addy.ke@rock-chips.com, Russell King , linux-kernel@vger.kernel.org, dianders@chromium.org, Kever Yang , linux-rockchip@lists.infradead.org, xjq@rock-chips.com, cf@rock-chips.com, hj@rock-chips.com, sonnyrao@chromium.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add basic rk3288 smp support, cpu 1~3 are in wfe state when get into kernel. Signed-off-by: Heiko Stuebner Signed-off-by: Kever Yang --- Changes in v2: - use rk3288_boot_secondary instead ofsmp_boot_secondary - discards the power domain operation - handle the per cpu starup when actived by 'sev' arch/arm/mach-rockchip/core.h | 1 + arch/arm/mach-rockchip/headsmp.S | 14 +++++++++ arch/arm/mach-rockchip/platsmp.c | 63 ++++++++++++++++++++++++++++++++++++---- 3 files changed, 72 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h index 39bca96..13de05a 100644 --- a/arch/arm/mach-rockchip/core.h +++ b/arch/arm/mach-rockchip/core.h @@ -18,3 +18,4 @@ extern char rockchip_secondary_trampoline_end; extern unsigned long rockchip_boot_fn; extern void rockchip_secondary_startup(void); +extern void rk3288_secondary_startup(void); diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S index 73206e3..bacdb56 100644 --- a/arch/arm/mach-rockchip/headsmp.S +++ b/arch/arm/mach-rockchip/headsmp.S @@ -20,6 +20,20 @@ ENTRY(rockchip_secondary_startup) b secondary_startup ENDPROC(rockchip_secondary_startup) +ENTRY(rk3288_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + mov r2, #3 + and r0, r0, r2 + ldr r1, =0xff700000 + ldr r1, [r1] + cmp r0, r1 + beq 2f + ldr r2, =0xfffd0000 + mov pc, r2 +2: + b secondary_startup +ENDPROC(rk3288_secondary_startup) + ENTRY(rockchip_secondary_trampoline) ldr pc, 1f ENDPROC(rockchip_secondary_trampoline) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 189684f..022a01d 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -60,7 +60,7 @@ static void pmu_set_power_domain(int pd, bool on) * Handling of CPU cores */ -static int __cpuinit rockchip_boot_secondary(unsigned int cpu, +static int __cpuinit rk3066_boot_secondary(unsigned int cpu, struct task_struct *idle) { if (!sram_base_addr || !pmu_base_addr) { @@ -80,6 +80,28 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, return 0; } +static int __cpuinit rk3288_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + if (!sram_base_addr) { + pr_err("%s: sram missing for cpu boot\n", __func__); + return -ENXIO; + } + + if (cpu >= ncores) { + pr_err("%s: cpu %d outside maximum number of cpus %d\n", + __func__, cpu, ncores); + return -ENXIO; + } + /* start the core */ + writel(virt_to_phys(rk3288_secondary_startup), sram_base_addr + 8); + writel(0xDEADBEAF, sram_base_addr + 4); + writel(cpu, sram_base_addr + 0); + dsb_sev(); + + return 0; +} + /** * rockchip_smp_prepare_sram - populate necessary sram block * Starting cores execute the code residing at the start of the on-chip sram @@ -125,7 +147,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) return 0; } -static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) +static void __init rk3066_smp_prepare_cpus(unsigned int max_cpus) { struct device_node *node; unsigned int i; @@ -194,12 +216,41 @@ static void rockchip_cpu_die(unsigned int cpu) } #endif -static struct smp_operations rockchip_smp_ops __initdata = { - .smp_prepare_cpus = rockchip_smp_prepare_cpus, - .smp_boot_secondary = rockchip_boot_secondary, +static void __init rk3288_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram"); + if (!node) { + pr_err("%s: could not find sram dt node\n", __func__); + return; + } + + sram_base_addr = of_iomap(node, 0); + if (!sram_base_addr) { + pr_err("%s: could not map pmu registers\n", __func__); + return; + } + + ncores = 4; +} + +static struct smp_operations rockchip3066_smp_ops __initdata = { + .smp_prepare_cpus = rk3066_smp_prepare_cpus, + .smp_boot_secondary = rk3066_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = rockchip_cpu_kill, + .cpu_die = rockchip_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip3066_smp_ops); + +static struct smp_operations rockchip3288_smp_ops __initdata = { + .smp_prepare_cpus = rk3288_smp_prepare_cpus, + .smp_boot_secondary = rk3288_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = rockchip_cpu_kill, .cpu_die = rockchip_cpu_die, #endif }; -CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); +CPU_METHOD_OF_DECLARE(rk3288_smp, "rockchip,rk3288-smp", &rockchip3288_smp_ops);