From patchwork Wed Sep 24 01:55:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: addy ke X-Patchwork-Id: 4961201 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3E6669F2BB for ; Wed, 24 Sep 2014 01:56:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5208320259 for ; Wed, 24 Sep 2014 01:56:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5DA0B200D6 for ; Wed, 24 Sep 2014 01:56:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XWbp0-0006vg-JA; Wed, 24 Sep 2014 01:56:46 +0000 Received: from regular1.263xmail.com ([211.150.99.134]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XWbor-0006rw-FE; Wed, 24 Sep 2014 01:56:38 +0000 Received: from addy.ke?rock-chips.com (unknown [192.168.167.157]) by regular1.263xmail.com (Postfix) with SMTP id CB8834E73; Wed, 24 Sep 2014 09:56:08 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from addy-vm.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id D06AB1B5A1; Wed, 24 Sep 2014 09:56:02 +0800 (CST) X-RL-SENDER: addy.ke@rock-chips.com X-FST-TO: wsa@the-dreams.de X-SENDER-IP: 127.0.0.1 X-LOGIN-NAME: addy.ke@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: kfx@rock-chips.com X-DNS-TYPE: 1 Received: from addy-vm.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) whith ESMTP id 28546TWAXPG; Wed, 24 Sep 2014 09:56:02 +0800 (CST) From: Addy Ke To: wsa@the-dreams.de, max.schwarz@online.de, heiko@sntech.de, olof@lixom.net, dianders@chromium.org Subject: [PATCH] i2c: rk3x: adjust the LOW divison based on characteristics of SCL Date: Wed, 24 Sep 2014 09:55:43 +0800 Message-Id: <1411523743-3444-1-git-send-email-addy.ke@rock-chips.com> X-Mailer: git-send-email 1.8.3.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140923_185637_871406_14801361 X-CRM114-Status: UNSURE ( 8.16 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: huangtao@rock-chips.com, Addy Ke , hl@rock-chips.com, yzq@rock-chips.com, zyw@rock-chips.com, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, linux-rockchip@lists.infradead.org, xjq@rock-chips.com, linux-i2c@vger.kernel.org, caesar.wang@rock-chips.com, cf@rock-chips.com, hj@rock-chips.com, zhengsq@rock-chips.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As show in I2C specification: - Standard-mode: the minimum HIGH period of the scl clock is 4.0us the minimum LOW period of the scl clock is 4.7us - Fast-mode: the minimum HIGH period of the scl clock is 0.6us the minimum LOW period of the scl clock is 1.3us - Fast-mode plus: the minimum HIGH period of the scl clock is 0.26us the minimum LOW period of the scl clock is 0.5us - HS-mode(<1.7MHz): the minimum HIGH period of the scl clock is 0.12us the minimum LOW period of the scl clock is 0.32us - HS-mode(<3.4MHz): the minimum HIGH period of the scl clock is 0.06us the minimum LOW period of the scl clock is 0.16us I have measured i2c SCL waveforms in fast-mode by oscilloscope on rk3288-pinky board. the LOW period of the scl clock is 1.3us. It is so critical that we must adjust LOW division to increase the LOW period of the scl clock. Thanks Doug for the suggestion about division formula. Signed-off-by: Addy Ke --- drivers/i2c/busses/i2c-rk3x.c | 79 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 72 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index 93cfc83..49d67b7 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -428,18 +428,83 @@ out: return IRQ_HANDLED; } +static void rk3x_i2c_get_ratios(unsigned long scl_rate, + unsigned long *high_ratio, + unsigned long *low_ratio) +{ + /* As show in I2C specification: + * - Standard-mode: + * the minimum HIGH period of the scl clock is 4.0us + * the minimum LOW period of the scl clock is 4.7us + * - Fast-mode: + * the minimum HIGH period of the scl clock is 0.6us + * the minimum LOW period of the scl clock is 1.3us + * - Fast-mode plus: + * the minimum HIGH period of the scl clock is 0.26us + * the minimum LOW period of the scl clock is 0.5us + * - HS-mode(<1.7MHz): + * the minimum HIGH period of the scl clock is 0.12us + * the minimum LOW period of the scl clock is 0.32us + * - HS-mode(<3.4MHz): + * the minimum HIGH period of the scl clock is 0.06us + * the minimum LOW period of the scl clock is 0.16us + */ + if (scl_rate <= 100000) { + *high_ratio = 40; + *low_ratio = 47; + } else if (scl_rate <= 400000) { + *high_ratio = 6; + *low_ratio = 13; + } else if (scl_rate <= 1000000) { + *high_ratio = 26; + *low_ratio = 50; + } else if (scl_rate <= 1700000) { + *high_ratio = 12; + *low_ratio = 32; + } else { + *high_ratio = 6; + *low_ratio = 16; + } +} + +static void rk3x_i2c_calc_divs(unsigned long i2c_rate, unsigned long scl_rate, + unsigned long *divh, unsigned long *divl) +{ + unsigned long high_ratio, low_ratio; + unsigned long ratio_sum; + + rk3x_i2c_get_ratios(scl_rate, &high_ratio, &low_ratio); + ratio_sum = high_ratio + low_ratio; + + /* T_high = T_clk * (divh + 1) * 8 + * T_low = T_clk * (divl + 1) * 8 + * T_scl = T_high + T_low + * T_scl = 1 / scl_rate + * T_clk = 1 / i2c_rate + * T_high : T_low = high_ratio : low_ratio + * ratio_sum = high_ratio + low_ratio + * + * so: + * divh = (i2c_rate * high_ratio) / (scl_rate * ratio_sum * 8) - 1 + * divl = (i2c_rate * low_ratio) / (scl_rate * ratio_sum * 8) - 1 + */ + *divh = DIV_ROUND_UP(i2c_rate * high_ratio, scl_rate * ratio_sum * 8); + if (*divh) + *divh = *divh - 1; + + *divl = DIV_ROUND_UP(i2c_rate * low_ratio, scl_rate * ratio_sum * 8); + if (*divl) + *divl = *divl - 1; +} + static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate) { unsigned long i2c_rate = clk_get_rate(i2c->clk); - unsigned int div; + unsigned long divh, divl; - /* set DIV = DIVH = DIVL - * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1)) - * = (clk rate) / (16 * (DIV + 1)) - */ - div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1; + rk3x_i2c_calc_divs(i2c_rate, scl_rate, &divh, &divl); - i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV); + i2c_writel(i2c, (divh << 16) | (divl & 0xffff), REG_CLKDIV); } /**