From patchwork Fri Oct 10 05:23:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 5063641 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 73A36C11AC for ; Fri, 10 Oct 2014 05:24:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A15252024F for ; Fri, 10 Oct 2014 05:24:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6810B2022D for ; Fri, 10 Oct 2014 05:24:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XcSgp-0004XU-5N; Fri, 10 Oct 2014 05:24:31 +0000 Received: from mail-pa0-x230.google.com ([2607:f8b0:400e:c03::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XcSgh-0004TR-57; Fri, 10 Oct 2014 05:24:23 +0000 Received: by mail-pa0-f48.google.com with SMTP id eu11so1023807pac.21 for ; Thu, 09 Oct 2014 22:24:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=GhHFbBQBMy+SHquPRuKjfRiZZ8zD1bBRq+OaaOj6ARE=; b=lAWK8mQPKiBX0HtSY/xKJw0e+nbCZBFucZ+Fdb1AkRJVeAv+emlOdPSE2V8oOuxrNs X4KOFOpYAYH2Irx0KYZCe5+z7SgsIr/eF+WHucduYRp58+R988Ujz0bX+vPpshepFnfo LLQ4JphEuvxce75SIjG/zFePdMHo2rCsAYyOzobH1TbmyxHfcnnBrV+ahKRHY5nnycDL gmi5Zhwt1uPHgtZJW9tmT+guhxmcB6be2WSGbsd1lVSUGkZvrGyWW8vX68B8PIVIlvQK FwBMEL15b2/AtMFkgIG9nh21CzFoikBfsajdnJoSmKq8aWU7FocW22QREof1/OwAf+xI i8Sw== X-Received: by 10.68.65.6 with SMTP id t6mr2747139pbs.138.1412918640505; Thu, 09 Oct 2014 22:24:00 -0700 (PDT) Received: from kever-X240.corp.google.com (dhcp-172-22-52-129.mtv.corp.google.com [172.22.52.129]) by mx.google.com with ESMTPSA id we3sm2244071pab.21.2014.10.09.22.23.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Oct 2014 22:24:00 -0700 (PDT) From: Kever Yang To: heiko@sntech.de, Mike Turquette Subject: [PATCH] clk: rockchip: change PLL setting for better clock jitter Date: Thu, 9 Oct 2014 22:23:57 -0700 Message-Id: <1412918637-9843-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141009_222423_218986_6476CA95 X-CRM114-Status: GOOD ( 11.03 ) X-Spam-Score: -0.7 (/) Cc: huangtao@rock-chips.com, dkl@rock-chips.com, addy.ke@rock-chips.com, linux-kernel@vger.kernel.org, dianders@chromium.org, Kever Yang , linux-rockchip@lists.infradead.org, xjq@rock-chips.com, cf@rock-chips.com, hj@rock-chips.com, sonnyrao@chromium.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we use 594MHz for clock source of dclk_vop0/1. HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit: TMDS clock(MHz) CTS require jitter (ps) 297 84.2 148.5 168 74.25 336 27 1247 PLL BW and VCO frequency effects the jitter of PLL output clock, clock jitter is better if BW is lower or VCO frequency is higher. If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4), the TMDS Clock jitter is higher than 250ps, which means we can't pass the test when TMDS clock is 297MHz or 148.5MHz. If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1), the TMDS Clock jitter is about 60ps and we can pass all test case. So we need this patch to make hdmi si test pass. Signed-off-by: Kever Yang Reviewed-by: Doug Anderson --- drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/clk/rockchip/clk.h | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 7c30a5a..11a7376a 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -83,7 +83,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 742500000, 8, 495, 2), RK3066_PLL_RATE( 696000000, 1, 58, 2), RK3066_PLL_RATE( 600000000, 1, 50, 2), - RK3066_PLL_RATE( 594000000, 2, 198, 4), + RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1), RK3066_PLL_RATE( 552000000, 1, 46, 2), RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 500000000, 3, 125, 2), diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index f4791fb..fd7be53 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -62,6 +62,15 @@ enum rockchip_pll_type { .bwadj = (_nf >> 1), \ } +#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \ +{ \ + .rate = _rate##U, \ + .nr = _nr, \ + .nf = _nf, \ + .no = _no, \ + .bwadj = _bw, \ +} + struct rockchip_pll_rate_table { unsigned long rate; unsigned int nr;