From patchwork Mon Nov 3 19:05:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soren Brinkmann X-Patchwork-Id: 5219201 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E4DE4C11AC for ; Mon, 3 Nov 2014 19:07:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF7202012F for ; Mon, 3 Nov 2014 19:07:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07E6E20127 for ; Mon, 3 Nov 2014 19:07:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlMy7-0006h7-Kf; Mon, 03 Nov 2014 19:07:11 +0000 Received: from mail-qg0-x236.google.com ([2607:f8b0:400d:c04::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlMxT-0006Ga-Ki; Mon, 03 Nov 2014 19:06:32 +0000 Received: by mail-qg0-f54.google.com with SMTP id q108so9329338qgd.13 for ; Mon, 03 Nov 2014 11:06:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=HDf8KpP0jC9S4M/ihOyD2xmIkjbqKFS0Aea4K102Mnc=; b=FyXPKisQQPQ96du30LrmWAyZXK6UShhLQ35r4leMFlNBJTzM/yEc4/Mlw1efBGeqj4 +Jf9yFafHFwXsxw7f+a2RU4r2OpuW9G7sHdJEiNCJ/kb6h537LV4bKKWK0U/o0ArngDe V811B9UCICIFwHP+qlm4UZLUUMft703jEzsDk677PpXPgS3ubkpwE+x3ocXi34Di1KfX BIQs9Fsuo1SumQNhpgNpzamYHy3LbvY+Q/uPpGu2/661suC52vl8XIFPpE3gGScd9VNB 9JcND7Po5nTAS7hWKfXIY8cYxkuSUxYvZM8SleYMpBKWdEKbBZd240VrdMLOSdgU/HTC 7CAA== X-Received: by 10.224.74.135 with SMTP id u7mr8780708qaj.67.1415041567647; Mon, 03 Nov 2014 11:06:07 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id d32sm17526288qge.20.2014.11.03.11.06.06 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 03 Nov 2014 11:06:06 -0800 (PST) From: Soren Brinkmann To: Linus Walleij Subject: [PATCH 4/7] pinctrl: zynq: Document DT binding Date: Mon, 3 Nov 2014 11:05:28 -0800 Message-Id: <1415041531-15520-5-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415041531-15520-1-git-send-email-soren.brinkmann@xilinx.com> References: <1415041531-15520-1-git-send-email-soren.brinkmann@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141103_110631_755106_A13F7F35 X-CRM114-Status: GOOD ( 10.69 ) X-Spam-Score: -0.7 (/) Cc: Laurent Pinchart , Heiko Stuebner , linux-sh@vger.kernel.org, Michal Simek , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-arm-kernel@lists.infradead.org, Alessandro Rubini X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add documentation for the devicetree binding for the Zynq pincontroller. Signed-off-by: Soren Brinkmann --- .../bindings/pinctrl/xlnx,zynq-pinctrl.txt | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt new file mode 100644 index 000000000000..86a86b644e6c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt @@ -0,0 +1,90 @@ + Binding for Xilinx Zynq Pinctrl + +Required properties: +- compatible: "xlnx,zynq-pinctrl" +- syscon: phandle to SLCR +- reg: Offset and length of pinctrl space in SLCR + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Zynq's pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, slew rate, etc. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + groups, pins, function, bias-disable, bias-high-impedance, bias-pull-up, + slew-rate, low-power-disable, low-power-enable + + Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast + respectively. + + Valid values for groups are: + ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, + qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp, + spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp, + sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, + sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, + can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, + uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp, + ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp, + gpio0_0_grp - gpio0_53_grp + + Valid values for pins are: + MIO0 - MIO53 + + Valid values for function are: + ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, + spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, + sdio1, sdio1_pc, sdio1_cd, sdio1_wp, + smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, + i2c0, i2c1, ttc0, ttc1, swdt0, gpio0 + +The following driver-specific properties as defined here are valid to specify in +a pin configuration subnode: + - io-standard: Configure the pin to use the selected IO standard according to + this mapping: + 1: LVCMOS18 + 2: LVCMOS25 + 3: LVCMOS33 + 4: HSTL + +Example: + pinctrl0: pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + + pinctrl_uart1_default: pinctrl-uart1-default { + common { + groups = "uart1_10_grp"; + function = "uart1"; + slew-rate = <0>; + io-standard = <1>; + }; + + rx { + pins = "MIO49"; + bias-high-impedance; + }; + + tx { + pins = "MIO48"; + bias-disable; + }; + }; + };