From patchwork Tue Jul 21 20:41:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 6838161 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DCE05C05AC for ; Tue, 21 Jul 2015 20:42:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6EBA20648 for ; Tue, 21 Jul 2015 20:42:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F24F920320 for ; Tue, 21 Jul 2015 20:42:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZHeMb-0001S8-PK; Tue, 21 Jul 2015 20:42:09 +0000 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZHeMS-00012k-Po for linux-rockchip@lists.infradead.org; Tue, 21 Jul 2015 20:42:01 +0000 Received: by pachj5 with SMTP id hj5so125967844pac.3 for ; Tue, 21 Jul 2015 13:41:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=eVDNXv2BR+dkOyCa8F+kXv84iW17ppO2AUv9EbsaZhQ=; b=dnD/z+2u5aSn561yOqQ8IwyLZeyAbR3Gv5kD7RiLYubL0bePAIl/Kxpk81hQ7zuDQ/ eDxzjukCAePcH1uhA77UKvs5lr5eTI1N+sxkFP0Zs4PhfopNWlxvT5tBJvi05CarBlT+ R2/RCmCUzL7r+fGNCJ492CabtnMFq+G5xKBeQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=eVDNXv2BR+dkOyCa8F+kXv84iW17ppO2AUv9EbsaZhQ=; b=Uihh+JP5I7rWV3+Iaf7YxOb4wVNknjAVwDA//ms+BEI8YZdRsq8jXZiw7dRreyYpqC Sgtir25ba58dS6BBL7UDMivIYXqFxc9XRpnJ7aIxgbKhRX9Ub/go8d9mVif42Tx8hjPz pW7meUG7sKi7NHk3u3KbOxg5nYNTZGQW9DZEmz5twgchirUh12/J1Q+L5LhRfgJWe6rK K/qnWD6lxGhAjK3WArYw1s9BdL4jCkPCj3E8FN9Ib4tP/TM4tXsAxzJjQkcwtispwZNs TAqZWhlR9h33xfoxRe99J7V1hCTjCl+dBsbmD2erwj2NQ7vIfmoUDsiGIcdqQQcuHvaA tLig== X-Gm-Message-State: ALoCoQlLb0JF+heb9vlBGWBL8/omdI6oGoZtOzptyNOXbGQ1Ii3Dy7bq8g4F2XfhQamZLeDjbB12 X-Received: by 10.66.186.138 with SMTP id fk10mr75281727pac.75.1437511297403; Tue, 21 Jul 2015 13:41:37 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id de2sm29131335pdb.15.2015.07.21.13.41.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Jul 2015 13:41:36 -0700 (PDT) From: Douglas Anderson To: Stephen Boyd , Heiko Stuebner Subject: [PATCH] clk: rockchip: Fix PLL bandwidth Date: Tue, 21 Jul 2015 13:41:23 -0700 Message-Id: <1437511283-14216-1-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.4.3.573.g4eafbef X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150721_134200_864926_17E5C82E X-CRM114-Status: GOOD ( 14.34 ) X-Spam-Score: -2.0 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandru Stan , mturquette@baylibre.com, Douglas Anderson , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, ykk@rock-chips.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson Reviewed-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 18 +++++++++--------- drivers/clk/rockchip/clk-rk3188.c | 2 +- drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/clk/rockchip/clk.h | 8 ++++---- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 1f88dd1..96903ae 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -120,8 +120,8 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) #define RK3066_PLLCON0_NR_SHIFT 8 #define RK3066_PLLCON1_NF_MASK 0x1fff #define RK3066_PLLCON1_NF_SHIFT 0 -#define RK3066_PLLCON2_BWADJ_MASK 0xfff -#define RK3066_PLLCON2_BWADJ_SHIFT 0 +#define RK3066_PLLCON2_NB_MASK 0xfff +#define RK3066_PLLCON2_NB_SHIFT 0 #define RK3066_PLLCON3_RESET (1 << 5) #define RK3066_PLLCON3_PWRDOWN (1 << 1) #define RK3066_PLLCON3_BYPASS (1 << 0) @@ -207,8 +207,8 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, RK3066_PLLCON1_NF_SHIFT), pll->reg_base + RK3066_PLLCON(1)); - writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK, - RK3066_PLLCON2_BWADJ_SHIFT), + writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, + RK3066_PLLCON2_NB_SHIFT), pll->reg_base + RK3066_PLLCON(2)); /* leave reset and wait the reset_delay */ @@ -261,7 +261,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); const struct rockchip_pll_rate_table *rate; - unsigned int nf, nr, no, bwadj; + unsigned int nf, nr, no, nb; unsigned long drate; u32 pllcon; @@ -283,13 +283,13 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1; pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); - bwadj = (pllcon >> RK3066_PLLCON2_BWADJ_SHIFT) & RK3066_PLLCON2_BWADJ_MASK; + nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1; - pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), bwadj(%d:%d)\n", + pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", __func__, __clk_get_name(hw->clk), drate, rate->nr, nr, - rate->no, no, rate->nf, nf, rate->bwadj, bwadj); + rate->no, no, rate->nf, nf, rate->nb, nb); if (rate->nr != nr || rate->no != no || rate->nf != nf - || rate->bwadj != bwadj) { + || rate->nb != nb) { struct clk *parent = __clk_get_parent(hw->clk); unsigned long prate; diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index edbafbc..0abf22d 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -817,7 +817,7 @@ static void __init rk3188_clk_init(struct device_node *np) rate = pll->rate_table; while (rate->rate > 0) { - rate->bwadj = 0; + rate->nb = 1; rate++; } } diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index a8bad7d..0df5bae 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -84,7 +84,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 742500000, 8, 495, 2), RK3066_PLL_RATE( 696000000, 1, 58, 2), RK3066_PLL_RATE( 600000000, 1, 50, 2), - RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1), + RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), RK3066_PLL_RATE( 552000000, 1, 46, 2), RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 500000000, 3, 125, 2), diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 93ea335..dc8ecb2 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -83,16 +83,16 @@ enum rockchip_pll_type { .nr = _nr, \ .nf = _nf, \ .no = _no, \ - .bwadj = ((_nf) >> 1), \ + .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ } -#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \ +#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ - .bwadj = _bw, \ + .nb = _nb, \ } struct rockchip_pll_rate_table { @@ -100,7 +100,7 @@ struct rockchip_pll_rate_table { unsigned int nr; unsigned int nf; unsigned int no; - unsigned int bwadj; + unsigned int nb; }; /**