From patchwork Mon Aug 24 08:12:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 7061521 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0F0669F358 for ; Mon, 24 Aug 2015 08:14:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 26ED620735 for ; Mon, 24 Aug 2015 08:14:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C20820708 for ; Mon, 24 Aug 2015 08:14:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZTmtq-00055Q-Mp; Mon, 24 Aug 2015 08:14:38 +0000 Received: from lucky1.263xmail.com ([211.157.147.132]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZTmth-0004zw-MY; Mon, 24 Aug 2015 08:14:31 +0000 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.128]) by lucky1.263xmail.com (Postfix) with SMTP id 30D625826F; Mon, 24 Aug 2015 16:14:01 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id D51441F8B5; Mon, 24 Aug 2015 16:13:56 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <4847911dffa590e8a8a7028804517c16> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 1231964SEQP; Mon, 24 Aug 2015 16:13:57 +0800 (CST) From: Shawn Lin To: Heiko Stuebner , Stephen Boyd , Michael Turquette Subject: [PATCH] clk: rockchip: disable init state before mmc card initialization Date: Mon, 24 Aug 2015 16:12:26 +0800 Message-Id: <1440403946-13266-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150824_011430_890545_024D9627 X-CRM114-Status: UNSURE ( 6.24 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, Shawn Lin , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP mmc host controller's IO input/output timing is unpredictable if bootloader execute tuning for HS200 mode. It might make kernel failed to initialize mmc card in identification mode. The root cause is tuning phase and degree setting for HS200 mode in bootloader aren't applicable to that of identification mode in kernel stage. Anyway, we can't force all bootloaders to disable tuning phase and degree setting before into kernel. Simply disable it in rockchip_clk_register_mmc. Signed-off-by: Shawn Lin --- drivers/clk/rockchip/clk-mmc-phase.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c index e9f8df32..02b6f3d 100644 --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -38,6 +38,9 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, #define ROCKCHIP_MMC_DEGREE_MASK 0x3 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) +#define ROCKCHIP_MMC_INIT_STATE_DISABLE (0x1) +#define ROCKCHIP_MMC_INIT_STATE_SHIFT (0) +#define ROCKCHIP_MMC_INIT_STATE_MASK (0x1) #define PSECS_PER_SEC 1000000000000LL @@ -119,6 +122,21 @@ static const struct clk_ops rockchip_mmc_clk_ops = { .set_phase = rockchip_mmc_set_phase, }; +static void rockchip_clk_mmc_disable_init(struct rockchip_mmc_clock *mmc_clock) +{ + if (mmc_clock->shift != ROCKCHIP_MMC_INIT_STATE_SHIFT) + return; + + writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_DISABLE, + ROCKCHIP_MMC_INIT_STATE_MASK, + mmc_clock->shift), + mmc_clock->reg); + + pr_debug("%s: clear mmc init state to %d", __func__, + (readl(mmc_clock->reg) >> (mmc_clock->shift)) & + ROCKCHIP_MMC_INIT_STATE_MASK); +} + struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *reg, int shift) @@ -139,6 +157,8 @@ struct clk *rockchip_clk_register_mmc(const char *name, mmc_clock->reg = reg; mmc_clock->shift = shift; + rockchip_clk_mmc_disable_init(mmc_clock); + if (name) init.name = name;