From patchwork Wed Mar 9 18:44:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 8548421 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0F5DBC0553 for ; Wed, 9 Mar 2016 18:45:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 21B5F202A1 for ; Wed, 9 Mar 2016 18:45:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 326992021A for ; Wed, 9 Mar 2016 18:45:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1adj6k-0008JU-Fd; Wed, 09 Mar 2016 18:45:18 +0000 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1adj6Y-000764-Q7 for linux-rockchip@lists.infradead.org; Wed, 09 Mar 2016 18:45:08 +0000 Received: by mail-pf0-x235.google.com with SMTP id n5so9280951pfn.2 for ; Wed, 09 Mar 2016 10:44:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rn5WS3M+b6zFYY061VngNu0tXh49pMjIRv/lF59NJcE=; b=KnckbE0f0bOStRCV2PiONXKmcrUS3raFyXOxlRmnR4dxgpU8TPuj7n3mr9pGgDU/Tu RhtwhXT0R4wH8Akt6OwrKXKkfcrrac9rbQS9D1BoETEk3JqP47usEp245SoF34vuYB43 Suoti0zz8ij3ag2GeIin1ZfEjiHJJ9juE1Uds= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rn5WS3M+b6zFYY061VngNu0tXh49pMjIRv/lF59NJcE=; b=EsTOcOcFpsVtqRpoebz5UCau3lTvAPN6DyazZ9D7wOVjyWb9qTkqLskBzdtaUmIGoj gczF+INF+OU4EPXy4mJHBle//oB9D4C74Szu5UhaSnTm3vTIA0RAc9C5+zWSVPE1EKVU RlDGvKtqJLpqrv+LlX/P1T8657hHGsNfyaooi9wzT0766UPCl+kn3UfAa7hnEnJ6dFNn XwvlOwIfD4gmJpcOSqF+fruwe3tZdTSIffMUMmrg0PdrnTeqqAtqWc4/ucne606NVj9b 6wPU+ZQ4iLx+JNbjlNVtztakky6tJOjw70Q5RhrMR0a3leXRoa9fUpEEADsOo3nRbdXP 5FHQ== X-Gm-Message-State: AD7BkJKCjq8AHdvr8hlGW+ATJB5Ahxh/1yIqsQq9pXZoO+Vqqdsj+B83FfOk8iUl92Z3jg== X-Received: by 10.98.80.10 with SMTP id e10mr52233726pfb.141.1457549086068; Wed, 09 Mar 2016 10:44:46 -0800 (PST) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id x18sm14025451pfi.42.2016.03.09.10.44.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Mar 2016 10:44:45 -0800 (PST) From: Douglas Anderson To: Russell King , Will Deacon , Heiko Stuebner , Matthias Brugger Subject: [PATCH v2 2/3] ARM: errata: Workaround erratum A12 821420 Date: Wed, 9 Mar 2016 10:44:15 -0800 Message-Id: <1457549056-22359-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: <1457549056-22359-1-git-send-email-dianders@chromium.org> References: <1457549056-22359-1-git-send-email-dianders@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160309_104506_926793_5B576747 X-CRM114-Status: GOOD ( 12.08 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nicolas.pitre@linaro.org, f.fainelli@gmail.com, ard.biesheuvel@linaro.org, Anson.Huang@freescale.com, Douglas Anderson , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, olof@lixom.net, shawn.guo@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This erratum has a very simple workaround (set a bit in a register), so let's apply it. Apparently the workaround's downside is a very slight power impact. Note that applying this errata fixes deadlocks that are easy to reproduce with real world applications. The arguments for why this needs to be in the kernel are similar to the arugments made in the patch "Workaround errata A12 818325/852422 A17 852423". Signed-off-by: Douglas Anderson --- Changes in v2: - A12 821420 new for v2. arch/arm/Kconfig | 10 ++++++++++ arch/arm/mm/proc-v7.S | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a5e16e4e796b..c3e46c9aacf5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1171,6 +1171,16 @@ config ARM_ERRATA_818325_852422 Feature Register. This bit disables an optimisation applied to a sequence of 2 instructions that use opposing condition codes. +config ARM_ERRATA_821420 + bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" + depends on CPU_V7 + help + This option enables the workaround for the 821420 Cortex-A12 + (all revs) erratum. In very rare timing conditions, a sequence + of VMOV to Core registers instructions, for which the second + one is in the shadow of a branch or abort, can lead to a + deadlock when the VMOV instructions are issued out-of-order. + config ARM_ERRATA_852423 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" depends on CPU_V7 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 6cea0435f3f2..a7f9e7567878 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -368,6 +368,11 @@ __ca12_errata: orr r10, r10, #1 << 12 @ set bit #12 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_821420 + mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg + orr r10, r10, #1 << 1 @ set bit #1 + mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg +#endif b __errata_finish __ca17_errata: