From patchwork Wed Mar 30 20:03:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 8858711 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 826C7BF29F for ; Fri, 15 Apr 2016 20:59:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 963422026F for ; Fri, 15 Apr 2016 20:58:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B95CA20373 for ; Fri, 15 Apr 2016 20:58:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1arApO-0000jN-BG; Fri, 15 Apr 2016 20:58:58 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1alMN5-00064f-Qa; Wed, 30 Mar 2016 20:05:48 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 4A166185D; Wed, 30 Mar 2016 22:05:27 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (LFbn-1-2159-240.w90-76.abo.wanadoo.fr [90.76.216.240]) by mail.free-electrons.com (Postfix) with ESMTPSA id 595701836; Wed, 30 Mar 2016 22:05:02 +0200 (CEST) From: Boris Brezillon To: Thierry Reding , linux-pwm@vger.kernel.org Subject: [PATCH v5 26/46] pwm: sun4i: implement hardware readout Date: Wed, 30 Mar 2016 22:03:49 +0200 Message-Id: <1459368249-13241-27-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459368249-13241-1-git-send-email-boris.brezillon@free-electrons.com> References: <1459368249-13241-1-git-send-email-boris.brezillon@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160330_130544_359614_0FEFBDD8 X-CRM114-Status: GOOD ( 15.84 ) X-Spam-Score: -2.9 (--) X-Mailman-Approved-At: Fri, 15 Apr 2016 13:58:40 -0700 X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Milo Kim , Kamil Debski , Heiko Stuebner , linux-doc@vger.kernel.org, David Airlie , Mike Turquette , linux-fbdev@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Alexandre Belloni , Daniel Vetter , Lee Jones , linux-clk@vger.kernel.org, linux-leds@vger.kernel.org, Boris Brezillon , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, Alexander Shiyan , Jonathan Corbet , Robert Jarzmik , lm-sensors@lm-sensors.org, linux-rockchip@lists.infradead.org, Chen-Yu Tsai , Tomi Valkeinen , linux-input@vger.kernel.org, Jean-Christophe Plagniol-Villard , intel-gfx@lists.freedesktop.org, Guenter Roeck , Jean Delvare , Joachim Eastwood , Bryan Wu , Jani Nikula , Mark Brown , Jacek Anaszewski , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Ryan Mallon , Jingoo Han , Dmitry Torokhov , Stephen Boyd , Liam Girdwood , Hartley Sweeten , Richard Purdie , Kukjin Kim , Daniel Vetter , Maxime Ripard MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement ->get_state() instead of only initializing the polarity in the probe function. This implementation also takes care of keeping the PWM clk enabled if at least one of the PWM exported by the PWM chip is already enabled, which should prevent glitches. Signed-off-by: Boris Brezillon Reviewed-by: Alexandre Belloni --- drivers/pwm/pwm-sun4i.c | 74 ++++++++++++++++++++++++++++++++++++------------- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 03a99a5..34cb296 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -252,11 +252,65 @@ static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) clk_disable_unprepare(sun4i_pwm->clk); } +static void sun4i_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *pstate) +{ + struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); + unsigned int clk_rate = clk_get_rate(sun4i_pwm->clk); + int prescaler, prescalerid; + int ret; + u32 val; + + ret = clk_prepare_enable(sun4i_pwm->clk); + if (ret) { + dev_err(chip->dev, "Failed to enable PWM clock"); + return; + } + + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) + pstate->polarity = PWM_POLARITY_INVERSED; + else + pstate->polarity = PWM_POLARITY_NORMAL; + + if ((val & BIT_CH(PWM_EN, pwm->hwpwm)) && + (val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm))) + pstate->enabled = true; + else + pstate->enabled = false; + + pstate->period = 0; + pstate->duty_cycle = 0; + prescalerid = (val >> (PWMCH_OFFSET * pwm->hwpwm)) & PWM_PRESCAL_MASK; + prescaler = prescaler_table[prescalerid]; + if (prescaler) { + u64 timens; + + clk_rate /= prescaler; + + val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); + + timens = ((val >> 16) & PWM_PRD_MASK) + 1; + timens *= NSEC_PER_SEC; + do_div(timens, clk_rate); + pstate->period = timens; + + timens = val & PWM_DTY_MASK; + timens *= NSEC_PER_SEC; + do_div(timens, clk_rate); + pstate->duty_cycle = timens; + } + + clk_disable_unprepare(sun4i_pwm->clk); +} + static const struct pwm_ops sun4i_pwm_ops = { .config = sun4i_pwm_config, .set_polarity = sun4i_pwm_set_polarity, .enable = sun4i_pwm_enable, .disable = sun4i_pwm_disable, + .get_state = sun4i_pwm_get_state, .owner = THIS_MODULE, }; @@ -307,8 +361,7 @@ static int sun4i_pwm_probe(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm; struct resource *res; - u32 val; - int i, ret; + int ret; const struct of_device_id *match; match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev); @@ -345,24 +398,7 @@ static int sun4i_pwm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pwm); - ret = clk_prepare_enable(pwm->clk); - if (ret) { - dev_err(&pdev->dev, "failed to enable PWM clock\n"); - goto clk_error; - } - - val = sun4i_pwm_readl(pwm, PWM_CTRL_REG); - for (i = 0; i < pwm->chip.npwm; i++) - if (!(val & BIT_CH(PWM_ACT_STATE, i))) - pwm_set_polarity(&pwm->chip.pwms[i], - PWM_POLARITY_INVERSED); - clk_disable_unprepare(pwm->clk); - return 0; - -clk_error: - pwmchip_remove(&pwm->chip); - return ret; } static int sun4i_pwm_remove(struct platform_device *pdev)