| Message ID | 1465859076-4868-6-git-send-email-dianders@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Montag, 13. Juni 2016, 16:04:29 schrieb Douglas Anderson: > On rk3399 we'd like to be able to properly set corecfg registers in the > Arasan SDHCI component. Specify the syscon to enable that. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> as the whole devicetree-part of the emmc addition is in my queue for 4.8, I'll pick this patch after everything else has gone into some tree. Heiko
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a4383f359264..1b57e92e0093 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -220,6 +220,7 @@ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+)